Tech jobs

Agency for Science, Technology and Research

AI Assembly C++ CUDA Distributed Training +9 skills

Scientist (Multi Chiplet Heterogeneous Integration and High speed IO designer (SIP)), IME

Job Description Summary Seeking an experienced embedded /software engineer to design and optimize low-level compute kernels for Large Language Model (LLM) inference and training on custom RISC-V based silicon.…

jobs.ametek.com

AI Altium Embedded Systems Ethernet FPGA +6 skills

Senior Electrical Design Engineer

Senior

We are seeking an experienced Senior Electrical Design Engineer to support the development of current and next-generation cameras, imaging energy filters, specimen preparation equipment, and other electron microscopy…

careers.dolby.com

Automation Bash FPGA Image Processing MATLAB +9 skills

Sr FPGA Design Engineer

Full-timeSenior

Join the leader in entertainment innovation and help us design the future. At Dolby, science meets art, and high tech means more than computer code. As a member of the Dolby team, you’ll see and hear the results of…

Sr Engineer CAD Pre-Silicon Front End - Bangalore

On-siteAPACSenior

Accessibility Agentic AI AI Automation CAD +13 skills

Role Overview Velaura is building custom silicon for Physical and Embodied AI, and we are building it from a blank sheet. The automation our design and verification engineers use to get from RTL to a clean handoff…

Hubble Network

Open 61d North AmericaFull-timeSenior

Engineering Manager, Wireless and Digital Design

Bluetooth C++ Embedded Linux Ethernet Firmware +16 skills

The Wireless Systems Engineer will develop and implement algorithms for satellite-to-Bluetooth connectivity, focusing on system-level design, modeling, and simulation. The role involves cross-functional collaboration to build a global IoT network using off-the-shelf Bluetooth chips.

140K – 190K $

SoC Design Verification Engineer - Bangalore

Accessibility AI Automation Cloud C++ +9 skills

Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers…

Senior Design Verification Engineer - Bangalore

On-siteAPACSenior

Accessibility ADAS AI Automation Cloud +11 skills

Velaura is hiring a Senior Design Verification Engineer in Bangalore to verify its next-generation Physical AI SoC — building UVM/SystemVerilog testbenches, running formal, emulation, and FPGA prototyping, performing HW/SW co-verification, and debugging issues from RTL blocks to post-silicon.

Design Verification Engineer- CPU - Bangalore

Accessibility AI Cloud C++ FPGA +4 skills

Design Verification Engineer owning verification of a custom high-performance CPU (fetch, decode, load-store, caches) for Velaura's Physical AI SoC. Day to day: building SystemVerilog/UVM testbenches with C/C++, writing test and coverage plans, running regressions, and supporting emulation, FPGA prototyping, and pre-silicon bring-up.

Design Verification Engineer- AI Accelerator - Bangalore

Accessibility AI Cloud C++ LLM +7 skills

Design Verification Engineer owning verification of Velaura's custom AI acceleration hardware (matrix/vector compute engines) for its Physical AI SoC in Bangalore. Day to day: building SystemVerilog/UVM/C/C++ verification environments, developing GEMM/GEMV reference models, and verifying numerical precision, throughput, and performance per watt under LLM and vision workloads.

Design Verification Engineer - Bangalore

Accessibility ADAS AI Automation Cloud +11 skills

Design Verification Engineer verifying Velaura's next-generation Physical AI SoC in Bangalore: building UVM/SystemVerilog and C++ verification environments, running formal verification, emulation, and FPGA prototyping, and performing HW/SW co-verification and debug from RTL blocks through post-silicon.

RTL Designer - Bangalore

Accessibility ADAS AI Automation Cloud +7 skills

Role Overview We are looking for talented RTL Engineers to help build Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, performance modelers, software engineers,…

Optiver Private

FPGA Engineer

On-siteNorth America

Big Data C++ FPGA Machine Learning SystemVerilog +2 skills

Designs high-speed, low-latency FPGA hardware for Optiver's Automated Trading Systems team in Chicago, accelerating network infrastructure and trading components in VHDL, researching low-latency techniques, and integrating systems alongside traders and software developers.

200K – 200K $

SECURE IC - France

Lead Software Engineer

On-siteAPACLead

AI Automation Machine Learning PCIe Python +5 skills

Lead engineer at Cadence (posted under SECURE IC) in Noida who independently owns the design, development, and delivery of Formal Verification IPs — writing Verilog design models, SystemVerilog Assertions, and RTL for protocols like AXI, CHI, PCIe, and CXL, with Python/Tcl automation and EDA formal-verification tools.

Kepler Communications

RemoteNorth America Canada LMIA employer

FPGA Digital Design Engineer

Canada

Designs and implements FPGA code for Kepler's satellite digital payloads — either DSP algorithms for software-defined radios or embedded systems interfacing with processors — across the full design flow (simulation, synthesis, place & route, timing closure, hardware testing) using Xilinx FPGAs and HDLs like Verilog/SystemVerilog.

Accessibility Bash CAD Embedded Systems FPGA +7 skills

131K – 181K CAD

HPR

On-siteNorth AmericaInternshipIntern

FPGA Engineering Intern - Summer 2027

Embedded Systems FPGA Linux Perl Python +3 skills

HPR (Hyannis Port Research) builds ultra-low latency electronic trading and capital markets infrastructure as a managed service. This summer internship has you own an FPGA project through its full development life cycle and build tools that automate RTL and testbench generation, using Verilog/VHDL plus scripting languages like Python.

42 – 42 $ / hr

Cerebras Systems

On-siteNorth AmericaStaff H-1B sponsor history Canada LMIA employer

Senior Staff Design Verification Engineer

Agentic AI AI Automation Ccpa Cloud +9 skills

Design verification engineer at Cerebras Systems, defining verification strategies and building SystemVerilog/UVM testbenches, coverage plans and regression infrastructure for its wafer-scale AI chip, and debugging across simulation, emulation, and silicon bring-up. On-site in Sunnyvale, CA; requires 14+ years of DV experience. Pays $250k-$300k base.

250K – 300K $

Cerebras Systems

On-siteNorth America H-1B sponsor history Canada LMIA employer

Design Verification Engineer

Agentic AI AI Automation Ccpa Cloud +9 skills

Design Verification Engineer who builds verification strategies, UVM/SystemVerilog testbenches, and coverage plans for Cerebras' wafer-scale AI chips, running regressions and debugging across simulation, emulation, and silicon bring-up. Requires 3+ years of DV experience plus Python/Perl scripting; onsite in Sunnyvale, CA.

190K – 230K $

SiFive India Private Limited

Automation C++ FPGA Machine Learning Python +2 skills

Staff Design Verification Engineer – Cache Verification

Open 7d On-siteAPACStaff

Taiwan

Staff-level individual contributor at SiFive verifying L2/L3 cache and memory-subsystem functionality — cache coherency, ordering, and correctness — from block level through subsystem integration. Day-to-day involves building SystemVerilog/UVM testbenches, assertions, checkers, and coverage models, plus debugging issues across RTL and testbench layers.

SiFive India Private Limited

Open 7d On-siteNorth AmericaPrincipal

Principal Design Verification Engineer – CPU Subsystem Power Management

Automation Machine Learning Python SystemVerilog Virtualization

Principal-level design verification engineer at SiFive leading verification of CPU-subsystem power management (DVFS, retention, clock gating, power gating, warm reset) for data-center-grade RISC-V cores, from test planning through subsystem signoff using SystemVerilog, formal, power-aware simulation, emulation, and Python automation.