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Principal engineer designing and verifying custom silicon chips for Microsoft's cloud infrastructure, using C/C++, SystemVerilog, UVM, and Python to ensure hardware quality and performance.
This internship role involves working on GPU design verification, emulation, and driver development for Apple Silicon SoCs. Interns will contribute to verification plans, testbench development, and emulation infrastructure using C/C++, scripting languages, and hardware description languages.
Apple is offering GPU internships in the UK focused on RTL design, power optimization, and physical design for Apple Silicon. Interns will collaborate with engineering teams on chip architecture, power analysis, and ASIC design flows using languages like C++, Python, and Verilog.
Designs and verifies complex ASICs for Google’s TPU hardware, focusing on AI/ML acceleration in data centers. Uses SystemVerilog/UVM to test digital logic, debug designs, and ensure functional correctness for next-gen data center accelerators.
About the Business Unit: Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer. Within the Wireless…
Silicon Quantum Computing (SQC) is at the forefront of global efforts to build the world’s first commercial-scale quantum computer, while delivering quantum-enhanced AI and simulation products to customers today.…
This role involves designing and maintaining verification plans and SystemVerilog/UVM testbenches for ARM's scalable coherent mesh network interconnects. Engineers will collaborate with architects to debug functional failures and improve verification methodologies for high-performance compute and AI applications.
Designs and verifies high-performance ASIC/SoC chip systems using Verilog/SystemVerilog, UVM, and RTL methodologies in a collaborative engineering environment.
Designs and implements high-performance digital logic for communication and optical networking chips using Verilog/SystemVerilog, guiding the RTL from specification to tapeout while collaborating with cross-functional teams.
Designs and verifies RTL (Verilog/SystemVerilog) for DSP and photonics ICs, focusing on high-speed datapaths and low-latency logic while collaborating with cross-functional teams.
Digital Design Engineer responsible for SoC/MCU digital sub-circuit development including RTL coding in Verilog/SystemVerilog, synthesis, STA, formal verification, DFT, and post-silicon validation at NXP's Catania site.
Lead the full digital IC design flow for complex SoC microcontrollers at NXP's Catania site, from architecture through RTL coding (Verilog/SystemVerilog), synthesis, STA, formal verification, and post-silicon debug.
ASIC Design Engineer working on mixed-signal chips for GPU power delivery and management, defining micro-architecture and developing RTL behavioral models through the full ASIC design flow to tape-out.
The Senior Design Engineer will design and verify high-performance RISC-V CPU cores for automotive and IoT SoCs. The role focuses on microarchitecture development, RTL coding, PPA optimization, and comprehensive functional verification.
This role involves developing and sustaining FPGA firmware and embedded software for flow cytometry instruments, focusing on high-throughput data acquisition and hardware control. The engineer will work with Verilog/SystemVerilog and embedded systems to ensure reliable instrument performance in a laboratory environment.
Designs and verifies PCIe controllers for NVIDIA’s GPUs/SOCs using UVM/Specman/e, building reusable testbenches and ensuring correctness via coverage-based methodologies.
Own FPGA firmware and embedded software for flow cytometry instruments, sustaining legacy Verilog/SystemVerilog codebases and building real-time acquisition pipelines on FPGA with embedded Linux/RTOS integration.
Develops and optimizes scalable front-end CAD methodologies and automation for Arm’s SoC design workflows, bridging RTL development and implementation. Focuses on improving build quality, efficiency, and cross-project consistency using EDA tools, Python, and AI-driven automation.
Senior FPGA Engineer designing and implementing ultra-low-latency FPGA architectures for real-time motion control, machine vision, and distributed EtherCAT-based automation platforms, using VHDL/Verilog/SystemVerilog on AMD/Xilinx or Intel/Altera devices.
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