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Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.
Student role assisting senior engineers with physical design tasks for cutting-edge AI semiconductor chips, including synthesis, floorplanning, and verification using industry-standard EDA tools.
Principal Product Application Engineer at Astera Labs designs and troubleshoots PCIe connectivity solutions for AI infrastructure, working with hyperscalers and OEMs to deploy high-speed retimers and influence product direction.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Designs and automates chip design flows for semiconductor connectivity solutions, using Python, Tcl, and EDA tools to optimize RTL generation and hardware development.
Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and automates semiconductor chip implementation flows, focusing on parasitic extraction and GenAI-driven methodologies to optimize high-speed AI connectivity chips from RTL to GDSII.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Junior Physical Design Engineer at Astera Labs in Tel Aviv builds and optimizes semiconductor chips for AI infrastructure, focusing on physical implementation, signoff, and automation using RTL-to-GDS flows and EDA tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Leads end-to-end physical design of high-performance AI infrastructure SoCs, owning floorplanning, timing, power, and signoff for advanced process nodes (7nm+) while mentoring engineers and collaborating with RTL, DFT, and analog teams.
About Bitdeer Technologies Group Bitdeer is a world-leading technology company for AI and Bitcoin mining infrastructure. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers and…
Backend engineer responsible for synthesis (RTL to gate-level), DFT tasks (scan insertion, ATPG, MBIST), and STA/timing closure on large-scale chips at 28nm or below, collaborating with RTL and PnR teams.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Designs and optimizes next-gen NAND Flash storage systems using FPGA architectures, focusing on RTL development, IP integration, and system validation for high-performance digital solutions.
Leads end-to-end physical implementation for advanced semiconductor and AI/HPC designs, optimizing PPA and reliability while collaborating with RTL, STA, DFT, and CAD teams to drive tape-outs.
Senior Physical Design Engineer responsible for full-chip and block-level physical implementation (RTL to GDSII) of next-gen transceiver IPs at TSMC 3nm/5nm nodes, using tools like ICC2, Innovus, and Calibre, with a focus on timing/power closure and tapeout signoff.
Drive post-silicon productization of bitcoin mining ASICs from bring-up through mass production, developing ATE test programs, optimizing yield, and performing silicon data analysis across cross-functional teams.
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