Tech jobs

REALTEK SINGAPORE PRIVATE LIMITED

Semi-Conductor Digital IC Design Engineer (IP Development)

Open 22d APAC

Singapore

Designs and develops semiconductor IP blocks for control or data paths, ensuring compliance with protocols and supporting SoC integration and verification.

Asic Linux Unix

Asic Ethernet PCIe SystemVerilog Uvm

Semi-Conductor Design Verification Engineer

Open 22d APACJunior

Singapore

Designs and verifies digital IP blocks and SoC architectures using SystemVerilog/UVM to ensure functional correctness of high-speed ASIC components like Ethernet switches and PCIe controllers.

NVIDIA

AI Asic Ethernet Networking PCIe +2 skills

Senior Chip Architect

Open 22d MENASenior

Israel

Define next-gen NIC and DPU chip architectures for NVIDIA’s networking unit, collaborating with GPU/CPU teams to optimize performance and debug full-chip correctness issues.

Hewlett Packard Enterprise

Director, ASIC Design & Front-End Implementation

Open 22d North America

AI Asic Automation CI/CD Cloud +5 skills

Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.

hpe

Director, ASIC Design & Front-End Implementation

Open 22d North America

AI Asic Automation CI/CD Cloud +5 skills

Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.

Google

TPU PCIe RTL Design Engineer

Open 23d North America

AI Asic Cloud Firmware GCP +9 skills

Designs and verifies PCIe subsystems and SoC infrastructure for Google’s next-gen TPUs, focusing on high-performance AI hardware acceleration.

163K – 236K $

Credo Technology Group

On-siteNorth AmericaContract

Associate Design Engineer

AI Analytics Asic Ethernet Fiber +3 skills

Team Credo is looking for an Associate Design Engineer to join our mission to transform the connectivity at scale. This role will be responsible for front-end ASIC design, including RTL implementation and verification…

GreenWave™ Radios

Open 49d North AmericaPrincipal

Principal Digital Design Engineer

Agentic AI AI Asic Claude Code C++ +12 skills

Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.

190K – 225K $

Google

Open 23d MENA, North AmericaLead

ASIC Design Verification Technical Lead, High-Speed DSP

Lead verification of high-speed DSP pipelines for Google’s TPU AI accelerators, ensuring pre-silicon models match physical silicon behavior using SystemVerilog/UVM and emulation.

AI Asic Cloud GCP Machine Learning +6 skills

240K – 333K $

Hudson River Trading

Open 78d North America, UK H-1B sponsor history

Physical Design Engineer

Design and optimize high-performance ASICs and FPGAs for low-latency trading systems, using industry-standard physical design tools and scripting to close timing and improve PPA.

AI Asic Automation Bash FPGA +4 skills

200K – 300K $

Apple

ASIC Design and Integration Engineer

Open 23d North America

Designs and integrates custom ASICs for Apple’s SoCs using SystemVerilog, RTL, and synthesis while collaborating with hardware and software teams.

Asic Rtl SystemVerilog

Open 24d APACFull-timeLead

Lead SoC Architect

AI Asic C++ Ethernet Firmware +6 skills

Design and oversee the System-on-Chip (SoC) architecture for AI-driven products, ensuring performance, power efficiency, and scalability.

RTL Design

Open 24d APACFull-time

Asic Automation Firmware FPGA Perl +6 skills

Designs and verifies RTL (Register Transfer Level) logic for AI hardware accelerators using Verilog/VHDL and industry-standard EDA tools.

ASIC RTL Design Engineer

Open 24d APACFull-time

Asic Automation Perl Python Rtl +3 skills

Designs and implements RTL for AI accelerators and ASICs, optimizing for performance and power efficiency.

ASIC RTL Design Engineer

Open 24d APACFull-time

Asic Rtl SystemVerilog Verilog

Designs and verifies RTL for AI accelerators and ASICs, optimizing hardware for machine-learning workloads.

Tower Research Capital

Open 28d HybridAPAC H-1B sponsor history

Hardware Engineer III

Asic Bash C++ Ethernet FPGA +10 skills

Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route market data efficiently.

NormalComputing

Open 62d HybridNorth AmericaFull-time

Hardware Engineer, RTL

Accessibility AI Asic Rtl SystemVerilog

Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across architecture, verification, and physical design to tape out custom ASICs.

Cisco

Agile AI Asic Automation Backbone.js +11 skills

Lab Operations Manager

Open 25d

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a…

NVIDIA