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Designs and maintains FPGA firmware, RTL modules, and device drivers while optimizing performance and debugging hardware-software integration for signal-processing systems.
Design and verify next-gen FPGA devices using UVM, SystemVerilog, and AI/ML-enabled methodologies; collaborate with emulation and SoC teams.
Designs and verifies high-performance FPGA subsystems for network test and measurement hardware using Verilog/SystemVerilog and industry-standard EDA tools.
Designs and optimizes CPU front-end RTL methodologies using AI tools to improve performance, power, and area for next-gen x86 processors.
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Designs and verifies digital semiconductor IP using Verilog/System Verilog, UVM, and Python/C++; performs CDC, DFT, and static timing checks; collaborates on verification test plans.
Designs and verifies semiconductor logic for communication chips using Verilog/SystemVerilog, CDC tools, and emulation platforms to ensure zero-defect silicon.
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Lead a team to design and deliver next-gen processor and SoC IP, driving RTL development, verification, and silicon execution while optimizing power, performance, and area.
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL, and PPA trade-offs with cross-functional teams.
Designs and verifies digital RTL subsystems for semiconductor products, using SystemVerilog/Verilog and collaborating with architecture and verification teams.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Designs ASIC microarchitectures using Verilog HDL, leads RTL architecture discussions, and ensures quality through synthesis, timing, and power analysis in hardware development.
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Design and verify FPGA-based hardware for Dolby’s cinema servers, audio processors, and HDR projection systems using VHDL/Verilog/SystemVerilog and advanced verification tools.
Principal Digital Engineer designs and implements DFT/Scan for automotive PMIC chips, working with RTL, synthesis, ATPG, and test teams to meet ASIL-B/D requirements and validate patterns on silicon.
Lead digital design for advanced RAIN RFID reader chips, owning RTL through tapeout and silicon validation while mentoring engineers and improving ASIC flows.
Principal Engineer defines and leads SoC/MCU architectures for India-focused semiconductor platforms, coordinating RTL design, verification, firmware, and validation to deliver first-pass silicon for automotive, industrial, and emerging domains.
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