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Schweitzer Engineering Laboratories, Inc. (SEL) designs, manufactures, and installs world-class products and solutions for use in critical infrastructure, making electric power safer, more reliable, and more…
Job Details: Job Description: The Role and Impact Join our team as an SoC Logic Design Engineer where you will play a critical role in developing Intel's next-generation Client System-on-Chip (SoC) products. In…
Job DescriptionJob Description Role Summary Southeastern Cyber LLC is seeking a Digital Design / Toolchain Engineer to extend our proprietary toolchains and pipelines. The engineer will integrate various policies into…
Apple Inc. is seeking a senior RTL design engineer to develop the MAC layer for wireless SoCs. You will translate system requirements into scalable microarchitecture and write area- and power-efficient RTL while…
Micron Technology is seeking a Principal RTL Design Engineer to lead the development of DRAM digital and mixed-signal IP, from architecture through silicon-ready signoff, delivering designs that meet power, performance…
ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
A senior IC engineer who architects and writes Verilog RTL for mixed-signal chips at Renesas, owns digital backend tasks like synthesis, static timing analysis, and logic equivalence checking, and mentors junior engineers. Requires 12+ years of ASIC/IC design experience with deep knowledge of the full design flow.
Principal Engineer designing wireless PHY/MAC silicon at InnoPhase IoT in San Jose: builds end-to-end simulation frameworks, DSP engines, and SystemVerilog RTL for WiFi/cellular physical layers, then drives designs through synthesis, timing closure, and verification with cross-team collaboration.
Senior analog/mixed-signal IC engineer who designs high-performance PLL and clock-generation circuits (integer-N, fractional-N, digital PLLs) for RF transceivers, SerDes, and high-speed I/O in advanced CMOS nodes. Day-to-day spans block-level design (VCO/DCO, charge pumps, dividers), Matlab/Simulink jitter modeling, transistor-level verification, and silicon bring-up and lab characterization.
ABOUT MDA SPACE Building the space between proven and possible, MDA Space is a trusted mission partner to the global space industry. A robotics, satellite systems and geointelligence pioneer with a 55-year+ story of…
Senior FPGA engineer implementing digital signal processing for software-defined radios on Zynq UltraScale+ MPSoC, using MATLAB/Simulink, VHDL/Verilog, and Xilinx Vivado in a hybrid role based in Boston or Scottsdale.
Designs and optimizes FPGA/ASIC hardware for low-latency trading systems using SystemVerilog, RTL, and vendor tool suites.
Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading…
Designs and verifies the digital logic inside Google's TPU AI accelerators: defining microarchitecture and writing high-quality SystemVerilog RTL for on-chip networks, then collaborating with verification, physical design, validation, and firmware teams to ship silicon. Core tech: SystemVerilog RTL, computer architecture, and ASIC design flows.
Job Summary: We are seeking an experienced Senior Principal Engineer - Digital Design to lead the micro-architecture, design, and execution of next-generation UA Link Switch solutions within the Memory Interface…
Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production. Drive SoC planning, integration strategy, execution schedules, risk management, and tape-out…
Senior project lead of a team of engineers in the tasks of guaranteeing specification compliance of analog & mixed signal design by means of advanced verification methodologies and concepts. It involves definition,…
Senior RTL/ASIC design engineer at SpaceX in Austin, TX developing next-generation ASICs for the Starlink satellite broadband system. Day to day: define micro-architecture, implement and integrate Verilog/SystemVerilog RTL, drive synthesis/timing closure with the implementation team, and support silicon bring-up and validation.
Senior RTL design engineer on SpaceX's Silicon Engineering team in Irvine, CA, developing next-generation ASICs for the Starlink satellite and ground network. Day to day: defining micro-architecture, implementing Verilog/SystemVerilog RTL, supporting synthesis/timing closure, and participating in silicon bring-up and validation.
Builds and maintains hardware emulation models for SambaNova’s AI workload accelerator (RDU), enabling pre-silicon software bring-up, performance verification, and verification acceleration. Works with RTL teams to ensure emulation-readiness, owns platform automation, and advises cross-functional teams on emulation strategy.
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