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Designs and verifies PCIe controllers for NVIDIA’s GPUs/SOCs using UVM/Specman/e, building reusable testbenches and ensuring correctness via coverage-based methodologies.
Own FPGA firmware and embedded software for flow cytometry instruments, sustaining legacy Verilog/SystemVerilog codebases and building real-time acquisition pipelines on FPGA with embedded Linux/RTOS integration.
Develops and optimizes scalable front-end CAD methodologies and automation for Arm’s SoC design workflows, bridging RTL development and implementation. Focuses on improving build quality, efficiency, and cross-project consistency using EDA tools, Python, and AI-driven automation.
Senior FPGA Engineer designing and implementing ultra-low-latency FPGA architectures for real-time motion control, machine vision, and distributed EtherCAT-based automation platforms, using VHDL/Verilog/SystemVerilog on AMD/Xilinx or Intel/Altera devices.
We are seeking a dedicated FPGA Digital Design Engineer to join our team. The FPGA Digital Design Engineer will be responsible for designing and implementing digital algorithms and systems processing. This role…
The RF Hardware Engineer will lead the design, development, and integration of custom radio and RF hardware for national security missions. The role involves the full development lifecycle, including circuit design, FPGA integration, and RF characterization using laboratory test equipment.
Staff Interface IP Verification Engineer (Pre-Silicon) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver…
Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
Lead or Senior ASIC/FPGA Design Verification Engineer owning verification scope, building UVM and SystemVerilog environments, and driving verification closure across Boeing's aerospace and defense programs.
SyoSil is hiring ASIC/FPGA design and verification engineers to work on RF radio ASIC projects using SystemVerilog and UVM. The role involves full-cycle IP block development, from architecture to verification, within a collaborative, SCRUM-based international team.
Design, implement, and verify digital integrated circuits and subsystems using RTL (Verilog/SystemVerilog) in a cross-functional semiconductor engineering team at Analog Devices in San Jose.
Designs and implements high-speed ASIC interconnect silicon, writing RTL and firmware to control analog blocks and ensure hardware-software integration through synthesis, emulation, and silicon bring-up.
RTL design and integration engineer on AMD's FPGA product team, driving silicon implementation using Verilog/SystemVerilog, EDA tools, and scripting automation.
Designs low-power digital circuits for brain-computer interfaces, including processors, accelerators, and radio components, using SystemVerilog, C/C++, and Python.
Designs and tests analog/mixed-signal integrated circuits for brain-machine interfaces, focusing on low-power, compact solutions using advanced CMOS FinFET technologies.
Designs and documents medium-to-complex FPGA modules for space applications (robotics, radar, telecom, DSP) by writing VHDL, synthesizing designs, and supporting verification/testing in a lab environment.
RTL Design Engineer developing TPU (Tensor Processing Unit) silicon for AI/ML hardware acceleration, using Verilog/SystemVerilog to design and verify ASIC blocks.
Design and implement real-time digital signal processing RTL in VHDL/SystemVerilog for Electronic Warfare and SIGINT systems, collaborating closely with RF hardware and embedded software teams.
Architect and implement digital logic embedded in power and analog ICs, owning the full flow from microarchitecture and RTL through synthesis, timing closure, DFT support, and silicon bring-up using Verilog/SystemVerilog.
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