Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Program manager oversees NVIDIA GPU chip bring-up from power-on to production, coordinating wafer forecasts, allocations, and cross-functional teams to meet silicon schedules and mitigate risks.
Design AI/ML-driven automation for ASIC chip development, using GenAI, reinforcement learning, and neural networks to optimize power, performance, and area for NXP’s processors.
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before…
Senior ASIC engineer designing on-chip interconnects and last-level caches for NVIDIA’s CPU and AI platforms, focusing on synthesis, timing closure, and performance optimization.
Leads a team to design and tape out next-gen processor and SoC IP, guiding RTL development, verification, and PPA optimization for high-performance, low-power ASICs.
Develops C++ tools and automated workflows for RTL generation and ASIC design at NVIDIA, improving Verilog RTL quality and connectivity algorithms for GPU and AI hardware.
Design and optimize custom silicon for AWS machine-learning servers, implementing high-performance RTL, microarchitecture, and trade-offs to power services like Inferentia.
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
Designs and optimizes SoC infrastructure IPs like interconnects, caches, and memory controllers for Qualcomm’s next-gen chips, balancing hardware-software trade-offs and collaborating with cross-functional teams.
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Designs and optimizes high-speed VLSI chips, collaborating with architecture and verification teams to reduce power consumption and ensure quality.
Design and optimize CPU physical layouts using synthesis, place & route, and timing/power analysis to meet PPA targets for Qualcomm's next-gen processors.
Design and implement high-speed chip micro-architectures for advanced networking ASICs, optimizing power and collaborating with global teams.
Senior ASIC Implementation Engineer, Low Power AI Location: Markham, Ontario, Canada Department: ASICS Engineering Work Location: onsite Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group >…
Designs and optimizes System-on-Chip (SoC) architectures for mobile/IoT/XR platforms, focusing on performance, power, and security trade-offs.
DSP Core Design Engineer, Principal Location: Hsinchu City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS…
Design and implement CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with architects and verification teams.
Architect high-performance ASICs for networking hardware, defining microarchitecture, RTL design, and silicon bring-up while balancing performance, power, and schedule constraints.
Designs and verifies FPGA circuits for automated trading infrastructure, developing in-house IP and scaling hardware globally.
Design and verify FPGA-based prototypes for Intel’s IP blocks, integrating and debugging RTL designs to enable early hardware and software validation.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
