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Movandi
4 views last week

Digital Design Engineer (Mid-Senior Level)

On-siteMENASenior
Saudi Arabia

Movandi, a 5G mmWave technology company, is hiring a Digital Design Engineer in Riyadh to own complex digital subsystems: leading RTL design and verification for FPGA/ASIC targets, driving microarchitecture and timing closure, and doing lab bring-up and debug. Core tools include SystemVerilog/VHDL, cocotb, Vivado, Cadence Genus/Innovus/Xcelium, Python/Tcl, and Git.

Automation Bash C++ Embedded Software Ethernet +16 skills
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Google Backed by Sequoia
3 views last week

ASIC Design Verification Manager, Google Cloud

North America Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.Licensed NL sponsor — This employer appears on the IND public register of recognised sponsors for work and highly skilled migrants. The recognition belongs to the employer and is not a commitment to sponsor this role.Denmark Fast-track company — This company is certified by SIRI for the Danish Fast-track scheme for hiring foreign skilled workers. The certification belongs to the employer and is not a commitment to sponsor this role.
United States

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…

AI Android Asic Bash Cloud +9 skills
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Apple Backed by Sequoia
3 views last week

SOC Design Verification Engineer

North America
United States

Verifies Apple's next-generation wireless SOC silicon: owns pre-silicon RTL verification from test planning through coverage closure and signoff, building reusable SystemVerilog/UVM testbenches across blocks like the CPU subsystem, PCIe, DMA, and MAC-PHY, including low-power/UPF verification and exploring AI-assisted verification workflows.

AI Assembly Bluetooth C++ Firmware +9 skills
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IonQ Backed by SoftBank Vision Fund
15 views last week

Staff Analog Mixed-Signal Design and Modelling Engineer

Open 80d UKContractStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United Kingdom

Design and implement Verilog-A/AMS models for cryo-CMOS ICs that control IonQ’s quantum processors, enabling simulations from room temperature down to a few kelvin.

Cloud Cmos Cybersecurity Financial Modeling MATLAB +5 skills
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IonQ Backed by SoftBank Vision Fund
12 views last week

Senior FPGA Verification Engineer

Open 58d HybridUKContractSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United Kingdom

Senior FPGA Verification Engineer develops and maintains advanced UVM/SystemVerilog test benches for quantum control systems, ensuring reliability and performance through constrained-random testing, coverage analysis, and CI pipelines.

Automation CI/CD Cloud Cybersecurity Financial Modeling +8 skills
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C_001 Transaction Network Services, Inc.
5 views last week

Senior FPGA Engineer (Verilog/Alveo U45N)

On-siteEuropeSenior
Hungary

Senior FPGA engineer at TNS's Waypoint Trading Solutions in Budapest, architecting and optimizing FPGA-based solutions (AMD Alveo U45N, Verilog/SystemVerilog, Vivado) for ultra-low-latency network monitoring, packet processing, and OpenNIC-based acceleration of global trading infrastructure on Linux.

Automation Backbone.js Bash C++ Ethernet +10 skills
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Ericsson
7 views last week

ASIC Design Verification Engineer

Open 112d HybridNorth America Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.

Asic Backbone.js Embedded Software Ethernet Git +10 skills
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Graphcore
9 views last week

Senior Silicon Logical Design Engineer - Bengaluru

Open 53d APACSenior Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
India

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed…

AI Automation Python Rtl SystemVerilog +1 skills
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Graphcore
7 views last week

Director, Silicon Logical Design

Open 133d UK Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
United Kingdom

Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.

AI Automation Program Management Python Rtl +3 skills
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Microsoft
5 views last week

Design Verification Engineer

Open 73d On-siteNorth AmericaFull-time
United States

Design Verification Engineer builds and runs testbenches to verify custom silicon components for Microsoft’s cloud infrastructure using SystemVerilog, UVM, and scripting.

Azure Cloud C++ Express.js Firmware +10 skills
102K – 202K $
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Graphcore
6 views last week

Director, Silicon Verification

Open 133d UK Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
United Kingdom

Leads a global team to define and execute verification strategies for Graphcore’s AI accelerator chips, ensuring high-quality silicon delivery using SystemVerilog, Python, and modern verification flows.

AI Assembly Automation C++ FPGA +15 skills
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Graphcore
9 views last week

Logical Design Engineer

Open 107d UK Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
United Kingdom

Designs and implements micro-architecture and RTL for AI chips, collaborating with cross-functional teams to deliver high-quality silicon solutions using SystemVerilog/VHDL and EDA tools.

AI Automation Python SystemVerilog Tcl +1 skills
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Graphcore
3 views last week

Staff Silicon Logical Design Engineer - Bengaluru, Multiple Vacancies

Open 99d APACStaff Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
India

Designs and integrates advanced semiconductor logic for AI chips in Bengaluru, using SystemVerilog, Python, and digital design flows to deliver RTL and microarchitecture for Graphcore’s silicon.

AI Automation Python Rtl SystemVerilog +1 skills
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Google Backed by Sequoia
3 views last week

SOC and IP Design Engineer, Google Cloud

MENA Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.Licensed NL sponsor — This employer appears on the IND public register of recognised sponsors for work and highly skilled migrants. The recognition belongs to the employer and is not a commitment to sponsor this role.Denmark Fast-track company — This company is certified by SIRI for the Danish Fast-track scheme for hiring foreign skilled workers. The certification belongs to the employer and is not a commitment to sponsor this role.
Israel

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

AI Cloud FPGA GCP Machine Learning +4 skills
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SiFive India Private Limited
3 views last week

Senior Staff Design Verification Engineer – Coherent Interconnect

Open 9d On-siteNorth AmericaStaff
United States

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…

Automation FPGA Machine Learning Python QoS +1 skills
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Google Backed by Sequoia
4 views last week

Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

APACSenior Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.Licensed NL sponsor — This employer appears on the IND public register of recognised sponsors for work and highly skilled migrants. The recognition belongs to the employer and is not a commitment to sponsor this role.Denmark Fast-track company — This company is certified by SIRI for the Danish Fast-track scheme for hiring foreign skilled workers. The certification belongs to the employer and is not a commitment to sponsor this role.
India

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…

AI Cloud GCP Machine Learning Networking +4 skills
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Talenza
4 views last week

FPGA Engineer

HybridAPACFull-time
Australia

Salary: $200000.00 - $250000.00 p.a. + + super + bonus FPGA Engineer - Permanent - Sydney - Trading About the role: High-Frequency Trading firm $200,000 - $250,000 Base + Super + Bonus Sydney CBD Permanent Opportunity…

C++ Ethernet FPGA Networking Python +4 skills
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ARM Backed by SoftBank Vision Fund
7 views last week

Staff GPU Verification Engineer

Open 129d HybridMENAStaff Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
Israel

Job Overview: Join Arm's GPU Hardware Verification team in Ra’anana, Israel, and help shape the future of the world's most widely deployed GPU architecture — Mali™. As a Staff Hardware Verification Engineer,…

Accessibility AI Automation CI/CD GPU +4 skills
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ARM Backed by SoftBank Vision Fund
16 views last week

Verification Engineer - AI/ML

Open 129d HybridEurope Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
Sweden

Job Overview: Are you passionate about digital hardware verification? This is a fantastic opportunity to move into a team developing hardware to support Machine Learning and Artificial Intelligence, key technologies…

Accessibility AI C++ Machine Learning Neural Networks +3 skills
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ARM Backed by SoftBank Vision Fund
19 views last week

Pre-Silicon Validation (AI/ML)

Open 58d HybridUK Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
United Kingdom

System Test Engineer verifying next-generation AI/ML neural network hardware accelerators at Arm, designing test automation and working with emulation platforms (ZeBu/Palladium/Strato) and RTL (SystemVerilog).

Accessibility AI Automation Git Machine Learning +8 skills
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