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Design and verify digital IP modules and support SoC integration for automotive battery management systems using scripting (Python/TCL), synthesis, DFT, and STA.
Lead the full digital IC design flow for complex SoC microcontrollers at NXP's Catania site, from architecture through RTL coding (Verilog/SystemVerilog), synthesis, STA, formal verification, and post-silicon debug.
Manage the full RTL-to-GDS physical design flow for complex automotive semiconductor chips, driving block-level timing closure, low-power checks, and signoff using Synopsys/Cadence tools and Tcl/Perl/Python scripting.
Designs and optimizes digital chip backends, focusing on synthesis, DFT, and STA to ensure timing and power closure for large-scale chips.
Develops and optimizes scalable front-end CAD methodologies and automation for Arm’s SoC design workflows, bridging RTL development and implementation. Focuses on improving build quality, efficiency, and cross-project consistency using EDA tools, Python, and AI-driven automation.
Associate Systems Engineer Company: The Boeing Company Boeing Defense, Space, and Security (BDS), Space, Intelligence & Weapons Systems (SI&WS), is seeking an Associate Systems Engineer (Level 2) to support the…
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Designs and implements high-performance, low-power ASICs for 5G/6G telecom infrastructure using Cadence and Synopsys tools, focusing on floorplanning, place-and-route, and physical verification.
Manage and optimize real-time financial market data systems at TP ICAP's Parameta Solutions in Singapore—integrating, normalizing, and distributing OTC data feeds from exchanges and vendors using tools like Refinitiv RTDS, cloud platforms, and scripting languages.
Designs and implements large SoC physical layouts from RTL to GDSII, including floorplanning, place & route, power grids, and sign-off verification for high-performance chips.
This role involves developing and maintaining ASIC physical design flows and automation using tools like Cadence Innovus and Synopsys Fusion Compiler. The engineer will partner with design teams to ensure high-quality silicon implementation through floorplanning, timing closure, and signoff.
This role involves the design, development, and integration of analog circuit blocks for Flash-IP and analog compute-in-memory technology to support AI inference. The engineer will simulate and validate analog circuits while collaborating with cross-functional teams to ensure performance and reliability.
Group Overview The TP ICAP Group is a world leading provider of market infrastructure. Our purpose is to provide clients with access to global financial and commodities markets, improving price discovery, liquidity,…
Design, implement, and verify digital integrated circuits and subsystems using RTL (Verilog/SystemVerilog) in a cross-functional semiconductor engineering team at Analog Devices in San Jose.
RTL design and integration engineer on AMD's FPGA product team, driving silicon implementation using Verilog/SystemVerilog, EDA tools, and scripting automation.
Designs and documents medium-to-complex FPGA modules for space applications (robotics, radar, telecom, DSP) by writing VHDL, synthesizing designs, and supporting verification/testing in a lab environment.
The Staff SW QA Engineer will design and execute test strategies for cloud-based networking solutions, focusing on performance, scale, and automation. The role involves working with microservices, Kubernetes, and various networking protocols using languages like Python and Java.
The Senior Software QA Engineer will design and execute test strategies for cloud-based networking applications, focusing on performance, scale, and automation. The role involves working with microservices, containerization, and various networking protocols using languages like Python and Java.
The Market Data Engineer manages and optimizes real-time financial market data systems, ensuring data integrity and low-latency distribution. The role involves integrating data feeds, automating ingestion pipelines, and supporting infrastructure using Python, Linux, and cloud technologies.
The Senior Physical Design Engineer will plan, build, and execute physical design for complex chiplets in server SoCs using advanced technology nodes. The role involves driving design implementation from concept to tape-out, performing synthesis and place-and-route, and collaborating with cross-functional teams.
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