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The application window is expected to close on: 10/28/2026 Meet the Team Join Cisco's Silicon Operations Team and play a pivotal role in shaping the future of networking as the NPI Product Supply Chain Program…
What You'll Do We are looking for a talented and experienced Digital Design Engineer to join the Silicon One Optics Group (S1O) Digital Design Team and drive the digital design and integration of Cisco’s silicon…
Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: OVERVIEW We are seeking a highly motivated Firmware Engineer to design, develop, debug,…
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm's validation team is part of the central Global SoC digital hardware organization…
Job Description Senior FPGA / ASIC Design Engineers - 5G & Satellite Technology Spectrum IT Recruitment is working with a cutting-edge technology business in Southampton that is expanding its engineering team and…
Senior FPGA / ASIC Design Engineers - 5G & Satellite Technology Spectrum IT Recruitment is working with a cutting-edge technology business in Southampton that is expanding its engineering team and looking for…
Company: RF360 Singapore Pte., Ltd. Job Area: Engineering Group, Engineering Group > RFFE ASIC Design General Summary: Key Responsibilities Design, develop, and implement software solutions aligned with business and…
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Leads end-to-end execution of advanced-node ASIC products from concept to production, managing schedules, budgets, and cross-functional teams to deliver revenue-critical silicon on time and at scale.
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads the design and implementation of high-performance digital IPs and SoC subsystems for AI infrastructure connectivity chips using Verilog/SystemVerilog, CXL, PCIe, and Ethernet.
Senior silicon design verification engineer who plans, builds, and runs verification for AMD's graphics processor IP — writing directed and constrained-random tests, debugging RTL/firmware failures, and improving UVM-based verification methodology. Core stack: SystemVerilog/UVM, Verilog, C/C++, and simulation tooling in Linux (and some Windows) environments.
Engineer on Google's TPU silicon team verifying low-power aspects of custom AI/ML accelerator hardware: running post-layout low-power signoff, validating multi-voltage/UPF designs with tools like Synopsys VCLP, and debugging physical design, place & route, and clock tree issues through tapeout.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
There's no such thing as a "safe system" - only safer systems. Our Security team works to create and maintain the safest operating environment for Google's users and developers. As a Security Engineer,…
Technical lead for RTL design of networking ASICs in Google's Server Chip Design team: defining block-level architecture, coding and debugging RTL (Verilog/SystemVerilog/VHDL), running simulations and Lint/CDC/FV checks, and participating in synthesis, timing/power, and silicon bring-up from spec to production.
Manages and mentors a team of RTL design engineers developing compute-core IP for Google's Tensor Processing Units (TPUs), owning micro-architecture specs, design reviews, and cross-functional planning for power, performance, and timing. Requires deep ASIC/SystemVerilog chip design experience plus people-management background.
Company: Qualcomm Technologies International Ltd Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Job Overview Qualcomm is looking for an experienced CPU Physical Design…
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