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Develops low-level firmware for cutting-edge SSDs using C/C++, NVMe/PCIe/SATA standards, and Agile workflows while collaborating with hardware teams.
Design and implement a high-performance, low-power ASIC accelerator for AI inference, integrating CPU and custom IP blocks using Verilog/SystemVerilog and AMBA protocols.
Lead the verification of next-gen x86 CPU cores, architecting testbenches in SystemVerilog/C++ to validate cache, ISA, and low-power features for high-performance client processors.
Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Design and develop advanced ASIC chips for coherent optics in Nokia’s Optical Networks division, working within a global engineering team.
Drive Meta’s ASIC development by leading cross-functional teams to design and deliver custom silicon for infrastructure, aligning engineering with business goals.
Designs firmware architectures for next-gen SSDs, leading cross-functional teams to implement storage interfaces like NVMe and PCIe while optimizing performance, reliability, and power constraints in C/C++.
Leads end-to-end ASIC development programs at Micron, coordinating RTL, verification, PnR, and silicon validation while managing schedules, risks, and cross-functional teams.
Designs and implements high-performance, low-power security engines and RISC-V processor modules in RTL using Verilog/System-Verilog for NVIDIA’s AI and cybersecurity products.
Builds and scales automation for GPU development, refactoring hardware models and build systems using Python/C++ and modern software practices to reduce manual rework.
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping…
Designs and optimizes memory subsystems (caches, MMUs, DRAM controllers) for NVIDIA GPUs, balancing performance, power, and area while modeling and validating new features.
Verify GPU memory subsystem and interconnect IP designs using SystemVerilog/UVM, testplans, and coverage-driven flows to ensure correctness and performance.
Design and optimize FPGA fabric (interconnect, logic, memory, clocking) for Microchip’s embedded devices, collaborating with architecture and verification teams to deliver high-performance, low-power FPGA products.
Lead the verification of next-gen x86 CPU cores, architecting testbenches and coverage plans for high-performance, low-power processor features in a global team.
Position Summary: The Thermal Imaging Technology Platform Architect is an enterprise technical leader responsible for connecting customer system requirements, market opportunities, and technology platform capabilities…
Develop and enhance SONiC-based network operating systems, integrating gNMI/gNOI and OpenConfig YANG models, while containerizing services with Docker for high-performance data centre networking.
Design Verification Engineer at Cisco in Armenia builds and runs testbenches in SystemVerilog to validate ASIC designs, debug with DVE/Verdi, and script in Tcl/Python/Perl.
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
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