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Leads full-chip functional verification for Micron’s non-volatile memory designs using System Verilog, UVM, and coverage-driven methodology to ensure tape-out readiness.
Design and lead digital architectures for power-management ICs in automotive and industrial systems using Verilog/SystemVerilog, synthesis, and verification flows.
Staff Subsystem Design Engineer Job Overview Arm’s IP and Technology team in Solutions Engineering department evelop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud…
Principal Engineer to lead digital design, synthesis, and static timing analysis for high-speed ICs at advanced process nodes using Cadence/Synopsys tools.
Leads hardware/software co-verification for SoC devices using emulators (e.g., Cadence Palladium) and FPGAs, bridging RTL porting, firmware development, and system-level testing across pre- and post-silicon phases.
Architect and deploy hardware emulation platforms for next-gen HBM memory products, integrating AI-driven tools to accelerate pre-silicon validation and firmware bring-up.
Architect and lead validation of next-gen memory subsystems (DDR5, LPDDR5/6, HBM) for FPGAs, defining scalable methodologies and driving silicon bring-up, debug, and customer enablement.
About the role Lead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing. What you'll do Micro-architect and own…
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
Grow with us Silicon CAD CI/CD Automation Engineer - Austin, Texas This is an On-Site, Hybrid position This is not a remote work opportunity About Us: The Team is part of the Ericsson Silicon engineering unit,…
At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is…
Tech Lead Design Engineer Location: San Jose, California, United States Department: Board Validation Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By…
Designs and verifies RTL for AI NPUs, focusing on SoC blocks like interfaces, power management, and clocking using Verilog/SystemVerilog and scripting (Python/Tcl).
Design the hardware and software stack that powers Lumai’s optical AI accelerator, ensuring it meets the compute and memory demands of modern transformer models and other AI workloads.
Application Engineer I: Systems Verification - Emulation Location: BELO HORIZONTE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.
Designs and integrates System-on-Chip (SoC) components like power management and clock/reset, collaborates with engineers on RTL coding and verification, and supports ASIC design flow.
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
Junior DFT engineer at NXP developing automotive and industrial SoCs; writes RTL, implements scan/ATPG/MBIST test flows, and automates validation using scripting and AI.
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