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Lead ASIC design verification for complex networking SoCs at Cisco's Common Hardware Group, planning and executing verification strategies, mentoring engineers, and building scalable SystemVerilog/UVM environments across silicon development.
Design verification engineer building and running SystemVerilog/UVM testbenches to validate ASIC/FPGA/SoC designs for aerospace systems in El Segundo or Huntington Beach, CA.
Designs and verifies ASIC/FPGA digital hardware for aerospace/defense systems, focusing on RTL coding, architecture, and system integration under government security clearance.
Staff engineer builds formal verification environments and properties to exhaustively validate next-gen mobile GPU blocks, ensuring functional correctness and power gating for Samsung’s Xclipse GPU.
Research Fellow designing open-source RISC-V processors and AI accelerators, using Verilog/SystemVerilog and EDA tools to advance digital IC research and mentor students.
Leads chip design and integration for high-speed interface innovations, owning RTL development, timing closure, synthesis, verification, and tape-out processes in a small, senior team focused on PHY-adjacent digital design.
An internship designing RTL for HBM SoC logic die, collaborating with architecture/verification teams to implement high-performance SoC solutions and integrating AI-driven tools into workflows.
The Research Fellow will conduct research on open-source processor and AI accelerator architectures, focusing on RISC-V designs and EDA toolchains. The role involves designing digital ICs, optimizing hardware workflows, and publishing research findings within an academic environment.
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Own verification of custom AI accelerator hardware for matrix/vector compute engines, ensuring numerical correctness and performance under LLM workloads using SystemVerilog/UVM and reference models.
Designs and executes verification plans for a custom Physical AI SoC’s CPU, ensuring correctness, performance, and reliability of microarchitecture components (fetch/decode/cache) via SystemVerilog/UVM/C++ testbenches and real-world workload testing.
Designs and implements digital blocks and SoC components for next-gen chiplet power delivery systems, using Verilog/SystemVerilog and collaborating with verification and physical design teams.
DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly…
Principal RTL engineer owns the microarchitecture and SystemVerilog RTL for a major block of SambaNova’s AI accelerator chip, driving PPA trade-offs, timing closure, and tape-out while collaborating with architects and physical-design teams.
Qualis LLC is seeking an experienced FPGA/Digital Design Engineer to develop high-performance FPGA solutions for advanced RF and software-defined radio systems. The ideal candidate is a hands-on AMD/Xilinx FPGA…
Lead pre-silicon verification for SambaNova’s AI chips, owning methodology, testbenches, and tape-out readiness, then debug first silicon in the lab.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
The Silicon Design Staff Engineer will lead verification efforts for PCIe subsystem IP, developing testbench infrastructure and verification plans. The role requires extensive experience in ASIC design verification and proficiency in UVM and SystemVerilog to support high-performance interconnect development.
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