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Designs and implements high-performance, low-power ASICs for 5G/6G telecom infrastructure using Cadence and Synopsys tools, focusing on floorplanning, place-and-route, and physical verification.
Manage and optimize real-time financial market data systems at TP ICAP's Parameta Solutions in Singapore—integrating, normalizing, and distributing OTC data feeds from exchanges and vendors using tools like Refinitiv RTDS, cloud platforms, and scripting languages.
Designs and implements large SoC physical layouts from RTL to GDSII, including floorplanning, place & route, power grids, and sign-off verification for high-performance chips.
This role involves developing and maintaining ASIC physical design flows and automation using tools like Cadence Innovus and Synopsys Fusion Compiler. The engineer will partner with design teams to ensure high-quality silicon implementation through floorplanning, timing closure, and signoff.
This role involves the design, development, and integration of analog circuit blocks for Flash-IP and analog compute-in-memory technology to support AI inference. The engineer will simulate and validate analog circuits while collaborating with cross-functional teams to ensure performance and reliability.
Group Overview The TP ICAP Group is a world leading provider of market infrastructure. Our purpose is to provide clients with access to global financial and commodities markets, improving price discovery, liquidity,…
Design, implement, and verify digital integrated circuits and subsystems using RTL (Verilog/SystemVerilog) in a cross-functional semiconductor engineering team at Analog Devices in San Jose.
RTL design and integration engineer on AMD's FPGA product team, driving silicon implementation using Verilog/SystemVerilog, EDA tools, and scripting automation.
Designs and documents medium-to-complex FPGA modules for space applications (robotics, radar, telecom, DSP) by writing VHDL, synthesizing designs, and supporting verification/testing in a lab environment.
The Staff SW QA Engineer will design and execute test strategies for cloud-based networking solutions, focusing on performance, scale, and automation. The role involves working with microservices, Kubernetes, and various networking protocols using languages like Python and Java.
The Market Data Engineer manages and optimizes real-time financial market data systems, ensuring data integrity and low-latency distribution. The role involves integrating data feeds, automating ingestion pipelines, and supporting infrastructure using Python, Linux, and cloud technologies.
The Senior Physical Design Engineer will plan, build, and execute physical design for complex chiplets in server SoCs using advanced technology nodes. The role involves driving design implementation from concept to tape-out, performing synthesis and place-and-route, and collaborating with cross-functional teams.
Architect and implement digital logic embedded in power and analog ICs, owning the full flow from microarchitecture and RTL through synthesis, timing closure, DFT support, and silicon bring-up using Verilog/SystemVerilog.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Red Team Penetration Tester conducting offensive cybersecurity operations and penetration testing for U.S. Government/DoD systems using tools like Kali, Metasploit, Cobalt Strike, and NMAP.
Build and maintain low-latency market data pipelines that ingest, normalize, and distribute real-time financial data from exchanges and vendors to trading systems and clients.
Designs real-time FPGA-based image processing hardware for AR/HUD systems in defense and automotive, bridging sensor data and computational optics with strict latency constraints.
Overview Microsoft is the world’s center of expertise on topological quantum computing. We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure…
CPU Physical Design Engineer performing full physical design implementation from RTL to GDSII—synthesis, placement, routing, clock tree synthesis, timing/power analysis, and signoff—using Synopsys and Cadence EDA tools on high-performance Intel CPUs.
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