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Job Description Summary As a Lead FPGA Research Engineer within GE Vernova Advanced Research, you will architect and develop state-of-the-art embedded systems for real-time controls and industrial communication…
Job Description Summary As a Lead Embedded Computing Research Engineer at GE Vernova's Advanced Research Center, you will be responsible for architecting, implementing, and testing edge solutions for embedded…
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
The application window is expected to close on: 10/02/2026 This role requires the employee to work onsite at the San Jose, CA office location. Meet the Team Common Hardware Group (CHG) Power is a central team that…
Designs and integrates system-on-chip (SoC) components for memory and storage controllers, focusing on microarchitecture, RTL implementation, and third-party IP integration to support AI, data analytics, and edge computing.
Entry-level (2027 grads) hardware design engineer at a proprietary trading firm, designing FPGA/ASIC logic in SystemVerilog to build low-latency compute engines that transform market data in real time. Core stack: SystemVerilog, FPGA/ASIC tools, computer architecture, with C++/Python on Linux.
Champion Tenstorrent’s RISC-V CPU and AI accelerator IP to customers, translating complex architecture into wins while gathering market feedback to shape product roadmaps.
Senior ASIC design methodology engineer advancing RTL development, verification, and physical implementation flows for Tenstorrent's Tensix AI compute cores — owning static analysis (Lint, CDC, RDC, DFT), logic equivalency, SDC/UPF development, and RTL-to-GDS enablement. Hybrid role based in Toronto, ON.
Develops and optimizes firmware, drivers, and compute architectures for Waymo’s high-performance autonomous vehicle hardware, focusing on AI workloads and custom silicon.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Designs and implements RTL for the FPGA configuration controller in AMD's Adaptive SoCs, owning specs and driving blocks from concept through production silicon — coding, lint/CDC, synthesis, timing, verification, DFT, and physical design integration — using Verilog/SystemVerilog, AMBA interconnects, and standard ASIC CAD tools.
Design and develop FPGA-based control systems for quantum computers, implementing signal processing and real-time logic using Verilog/VHDL and Vivado.
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't…
Senior ASIC design verification engineer in Lund, Sweden: develops verification tests, testbench components and VIPs from scratch, maintains and integrates third-party VIPs, implements assertions and functional/code coverage, and analyzes results for complex ASIC designs in close collaboration with RTL designers and verification teams.
A senior ASIC design engineer who designs, verifies, brings up, and debugs digital subsystems in electro-optical SoCs for Ayar Labs' co-packaged optics that move data for AI systems. Day to day: RTL in Verilog/SystemVerilog, testbenches, timing constraints and documentation, and Python-driven silicon bring-up.
Owns and scales the front-end CAD/design automation flows for Ayar Labs' ASIC and SoC teams in Bengaluru: building Python/Tcl/Shell/Make tooling for lint, CDC/RDC, regressions, and signoff readiness, supporting Synopsys/Cadence/Siemens EDA deployments, and championing AI-assisted CAD agents and workflows.
Head of Business Development - Taiwan Location: Hsinchu, Taiwan (with regular travel to Taepei, Taichung, Tainan and periodic travel to San Jose, CA) Ayar Labs is shattering AI data bottlenecks by moving data at the…
Ayar Labs is hiring a hands-on ASIC engineer to design, verify, and bring up digital subsystems in electro-optical SoCs for its co-packaged optics products that move AI data over light. Day to day this means writing Verilog/SystemVerilog RTL, building testbenches, defining timing constraints, and debugging custom silicon with Python and firmware.
Sr. Staff Engineer designing and debugging digital subsystems for Ayar Labs' electro-optical ASICs (co-packaged optics that move AI data over light). Day to day: writing RTL in Verilog/SystemVerilog, building testbenches, defining timing constraints, and doing silicon bring-up/debug with Python, C/C++, and firmware — on-site in San Jose.
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