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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.
Leads the full lifecycle of ASIC chip development for AI infrastructure, coordinating cross-functional teams to design, fabricate, and validate semiconductor solutions.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
AMD is hiring a hands-on platform engineer to build and run the developer infrastructure and AI tooling behind its AI-assisted silicon design program — modernizing source control, CI/CD, compute/storage, plus telemetry and benchmarking for AI solutions. Core stack includes Python, Git/GitHub, Linux, Slurm/LSF, and LLM operations.
Qorvo is hiring a Principal Digital IC Design Engineer in Richardson, TX to lead full-flow ASIC development — from architecture and RTL (SystemVerilog) through synthesis, place & route, STA, physical verification, and silicon bring-up — using Synopsys/Cadence EDA toolchains and Python/TCL scripting.
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works…
Job ID: 113650 The Leonardo DRS Naval Power Systems business is a trusted provider of innovative naval gas and hybrid power systems, control technology and support solutions for the U.S. Navy and navies around the…
Change people’s lives and love what you do! Cochlear develops world-leading medical devices that help people hear. As a top 100 medical device company and market-leader in implantable hearing devices, more people…
Senior Digital Design Engineer at Omni Design Technologies working on the digital datapath and controllers of high-performance ADC/DAC data converters. Day-to-day covers RTL design and verification, behavioral modeling, synthesis, timing closure, and P&R support in advanced CMOS, using Verilog/SystemVerilog and Cadence tools like Genus, Tempus and Innovus.
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