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Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Entry-level digital design engineer on Silicon Labs' Wireless MCU Digital Design team in Austin, TX. Day to day: designing and validating digital logic blocks for low-power wireless SoCs — RTL development, simulation and verification, debugging, and silicon bring-up. Core tech: Verilog/SystemVerilog, VLSI/digital IC design, EDA tools.
Silicon Labs is hiring a design modeling engineer in Austin (hybrid) to build functional and performance models and virtual hardware platforms for its low-power wireless IoT connectivity SoCs. The role spans C/C++ modeling, architecture exploration, and application/driver-level software, working alongside hardware and software architects.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Designs, develops, and optimizes high-performance, ultra-low-latency FPGA compute and networking systems for electronic trading infrastructure, owning the full RTL flow from specification through synthesis and implementation, with verification support and mentoring. Uses SystemVerilog/VHDL, Linux, and tools like VCS/Verdi; full-time on-site in Needham, MA with no visa sponsorship.
Senior FPGA Design Engineer at HPR (Hyannis Port Research) builds and optimizes ultra-low-latency FPGA compute and networking systems for electronic trading infrastructure. Owns RTL design from specification through synthesis and implementation using SystemVerilog/VHDL on Linux, mentoring junior engineers. Full-time on-site in Needham, MA.
Tech Lead for front-end digital design of high-performance switch ASICs powering rack-scale AI infrastructure at Astera Labs. The role owns blocks from microarchitecture through GDS — RTL, synthesis, timing closure, gate-level simulation, DFT, verification, and silicon bring-up — using Synopsys/Cadence flows and protocols like PCIe Gen 6/7, Ethernet, UALink, and UCI.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
A senior hands-on role leading microarchitecture and RTL development for complex connectivity IPs/subsystems (PCIe, CXL, Ethernet, UALink, UCIe) at Astera Labs in Bengaluru, owning designs from spec through integration and post-silicon debug. Core technologies: SystemVerilog/Verilog, high-speed data paths, flow control, simulation, CDC, synthesis, and timing.
A technical manager role at Astera Labs in Tel Aviv owning RTL design execution for connectivity silicon blocks that power large AI clusters — taking features from microarchitecture through synthesis, timing closure, and tapeout using Verilog/SystemVerilog with PCIe, CXL, and Ethernet interconnect technologies.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
AMD is hiring a hands-on platform engineer to build and run the developer infrastructure and AI tooling behind its AI-assisted silicon design program — modernizing source control, CI/CD, compute/storage, plus telemetry and benchmarking for AI solutions. Core stack includes Python, Git/GitHub, Linux, Slurm/LSF, and LLM operations.
We are looking for a Senior Engineer (FPGA) to join a Radio & Communications division and play a key role in the design, architecture, and development of advanced communication systems. This role focuses on…
We are looking for a FPGA Engineer to join a Radio & Communications division and contribute to the design and development of advanced communication systems. This role focuses on FPGA-based modem implementation,…
We are looking for a Technical Lead Engineer (FPGA) to join a Radio & Communications division and drive the architecture, development, and delivery of advanced communication systems. This role focuses on FPGA-based…
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