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Leads the design and deployment of system-level test solutions for next-generation AI processors, including hardware, software, automation, and characterization to support silicon bring-up and manufacturing.
Turn Up Your Career — Lead the Charge in Home Theater Innovation with TCL! Passionate about next-level visuals and immersive sound? Ready to turn that excitement into impact? ActionLink is seeking a Market Development…
Power Growth. Inspire Teams. Put TCL Front and Center! Bring your leadership skills and sales expertise to a role where every day is an opportunity to influence results. As TCL's Market Development Manager,…
Make the Holidays Brighter with TCL and Help Shoppers Find Their Perfect Entertainment Upgrade! Looking for a seasonal role that blends your passion for technology and customer service? Join ActionLink as a Seasonal…
ASIC Design Verification engineer building UVM testbenches and driving IP/sub-system/SoC verification closure for Ethernet and high-speed networking data-center ASICs. Day to day: simulation, formal verification and emulation, coverage closure, debugging failures with design teams. Core stack: SystemVerilog, UVM, Verilog, AXI/APB, Python/C/C++.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…
Приглашаем в нашу команду Middle Database Developer (Oracle). Проект в финансовой и банковской сфере. Система обеспечивает основной бухгалтерский учет банка и полноценную автоматизацию обслуживания и ведения…
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and…
Design Engineer Intern (CCE2) Astera Labs · San Jose, CA · Internship · On-site About Astera Labs Astera Labs builds connectivity solutions that help power modern AI infrastructure. Compute Connectivity Engineering 2…
Designs and optimizes physical layouts for AI connectivity ASICs using EDA tools like Cadence/Synopsys, ensuring timing closure and signoff for complex SoCs in server/storage/networking applications.
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
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