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Build and optimize SAI/SDK for high-performance AI/HPC switch ASICs, integrating with SONiC and hardware drivers while leveraging AI-first development tools.
Build and optimize NOS platforms for high-performance AI/HPC switches, integrating SONiC and FBOSS with ASIC drivers, BSPs, and hardware bring-up in a Linux/C++/Python environment.
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Join Kyocera International, Inc. We’re hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education,…
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
What We’re Looking For: We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create…
Experienced Engineer - FPGA CAD Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Join our Team About this opportunity: You will join the FPGA CAD team to support design and…
Define and build low-level firmware for next-gen AI cluster switches, bridging silicon and orchestration software to maximize bandwidth, minimize latency, and ensure reliability across thousands of AI accelerators.
Lead a team in Bangalore to define and scale physical design methodologies and CAD flows for Microsoft’s custom silicon (Azure Cobalt and Maia), driving AI-driven automation and first-pass silicon success.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Define and implement firmware for next-gen AI cluster switches, bridging ASIC silicon with cluster orchestration software to maximize bandwidth, minimize latency, and ensure reliability across thousands of AI accelerators.
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Architects and implements power-analysis techniques for NVIDIA’s next-gen switches, using Verilog, Python, and industry tools to model and reduce chip energy consumption.
Designs and qualifies power systems for Cisco’s networking hardware, from IP phones to data-center switches, collaborating with cross-functional teams to meet performance, reliability, and regulatory requirements.
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Design and verify ASIC blocks and full chips for Cisco’s networking hardware using SystemVerilog/UVM, then bring up silicon and analyze performance.
Lead a team designing and integrating custom silicon accelerators for AWS’s ML inference chips, ensuring high-performance SOC design and on-time tape-outs.
Design and implement high-speed ASICs for networking routers and switches using Verilog/SystemVerilog, collaborating with physical design and verification teams to meet power, timing, and area targets.
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
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