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Job Description Successful applicant must be a U.S. with the ability to obtain a DoD Security Clearance Responsibilities Include: Perceptive Innovations is seeking a self-starting and experienced individual to be a…
Designs and validates high-bandwidth memory (HBM) and 3D-stacked DRAM architectures, working closely with U.S. customers to solve base-die challenges and optimize next-gen memory products.
Leads design and implementation of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT, co-developing DRAM-on-Logic configurations with U.S.-based customers and managing foundry verification and IP integration services. Day-to-day work centers on RTL design to implementation in Verilog/VHDL, memory PHY/controller IP, BIST/DFT, and physical design.
Designs 3D-stacked DRAM logic dies and digital IP for DRAM-on-Logic systems, collaborating with U.S. customers and foundries to optimize performance and integration.
Principal Design Verification Engineer at SpaceX to develop and verify next-generation ASICs for Starlink satellites and ground infrastructure, ensuring high-performance connectivity in space and global networks.
Principal Design Verification Engineer at SpaceX designs, verifies, and validates next-generation ASICs and FPGAs for Starlink’s satellite and ground infrastructure, ensuring high-performance connectivity.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, using SystemVerilog, UVM, and Python to ensure reliable satellite and ground infrastructure connectivity.
Design Verification Engineer at SpaceX developing and testing next-generation ASICs for Starlink's satellite and ground infrastructure using SystemVerilog, UVM, and Python.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring satellite and ground infrastructure connectivity through pre- and post-silicon validation.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
A Summer 2027 hardware engineering internship at AMD in Edinburgh, UK, running full-time (hybrid or onsite) from June 1, 2027. The intern works alongside AMD experts on projects in the AI ecosystem, with desired exposure to digital logic design, RTL (VHDL/Verilog), DSP, and Xilinx FPGA tooling.
Designs and develops ASICs for optical transceivers in next-gen optical modems, focusing on HDL-based digital circuit implementation, synthesis, timing analysis, and RTL verification.
Principal Engineer leading post-silicon validation and testing of next-gen coherent DSP ASICs for AI and optical networking, ensuring first-silicon readiness and production deployment.
#WeAreIn for jobs that impact everyone's life. Build the future nobody’s dreamed of yet... are you ready to rethink the impossible? As a Principal Engineer DSP Design in our Research & Development team,…
Seasoned DSP Hardware Design expert with 7+ years of experience in taking complex digital signal processing solutions from RTL development to silicon. Strong expertise in Verilog RTL design, fixed-point arithmetic,…
Senior Digital Design Engineer on Murata Finland's ASIC Design Team in Vantaa, taking digital ASIC designs from early concept through mass production for safety-critical gyroscope and accelerometer sensors. Core work is Verilog/VHDL RTL design, design verification, and understanding the RTL-to-GDSII flow, in a hybrid work model.
Role Overview We're looking for a Senior Physical Design Engineer - Synth to own synthesis, timing convergence, and implementation readiness for key partitions across our AI accelerator roadmap. This is a hands-on…
Role Overview As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving…
Responsibilities: Develop design requirements for an NPU based on system-level specifications. Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and…
Job Description: 1. Responsible for micro-architecture design and RTL implementation of high-performance CPU front-end pipeline, including instruction fetch, branch prediction, instruction decode, dispatch and…
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