Tech jobs

Director, ASIC Design & Front-End Implementation

Open 23d North America

AI Asic Automation CI/CD Cloud +5 skills

Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.

Intel

Open 23d HybridNorth AmericaInternshipSenior

Senior EDA Tools Software Engineer

AI Analytics Automation CAD CI/CD +10 skills

Build and lead a new automation platform for SoC chassis design, translating architecture specs into generated RTL, registers, and verification collateral using Python and templating systems.

174K – 330K $

Synopsys

AI Assembly Bash Embedded Software Ethernet +8 skills

ASIC Digital Design, Staff Engineer-18334

Staff

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

Google

Open 24d North AmericaSenior

Senior CAD Engineer, RTL Design, Silicon, Google Cloud

AI Automation CAD Cloud GCP +6 skills

Design and verify custom silicon for Google’s TPU AI accelerators, leading CAD methodology and RTL design flows to power next-gen AI/ML systems.

163K – 236K $

River AI Inc.

Member of Technical Staff, Hardware, Performance Engineer

North America

AI Automation C++ CUDA Deep Learning +4 skills

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training…

River AI Inc.

Member of Technical Staff, Hardware, Design Verification Engineer

North America

AI Automation Bash CI/CD Deep Learning +8 skills

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training…

River AI Inc.

Member of Technical Staff, Hardware, RTL Design Engineer

North America

AI Assembly C++ Deep Learning Firmware +6 skills

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training…

Google

TPU PCIe RTL Design Engineer

Open 24d North America

AI Asic Cloud Firmware GCP +9 skills

Designs and verifies PCIe subsystems and SoC infrastructure for Google’s next-gen TPUs, focusing on high-performance AI hardware acceleration.

163K – 236K $

Google

Express.js PCIe Rtl SystemVerilog Verilog

Junior SoC IP Design Engineer, Google Cloud

Open 24d MENAJunior

Israel

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

Xpin AI

Accessibility AI API Cloud CSS +17 skills

Product Designer - UI/UX

Open 24d MENA

United Arab Emirates

Design bilingual AI interfaces for government and enterprise products in the GCC, focusing on clarity, trust, and RTL/English typography in Figma and related tools.

Renesas Electronics

Staff Engineer, Physical Design

Open 24d APACStaff

Agile Automation Perl Python Rtl +1 skills

Lead block- and subsystem-level physical design closure for complex SoCs, focusing on timing, congestion, power integrity, and clocking methodologies using tools like Synopsys ICC2 and Cadence Innovus.

Apple

ASIC Design and Integration Engineer

Open 24d North America

Designs and integrates custom ASICs for Apple’s SoCs using SystemVerilog, RTL, and synthesis while collaborating with hardware and software teams.

Asic Rtl SystemVerilog

Open 25d APACFull-timeLead

Lead SoC Architect

AI Asic C++ Ethernet Firmware +6 skills

Design and oversee the System-on-Chip (SoC) architecture for AI-driven products, ensuring performance, power efficiency, and scalability.

Open 25d APACFull-timeLead

RTL Micro Architect Lead

AI Firmware Rtl SystemVerilog Verilog

Leads RTL microarchitecture design for an AI-focused company, defining hardware blocks and optimizing chip performance for machine-learning workloads.

RTL Design

Open 25d APACFull-time

Asic Automation Firmware FPGA Perl +6 skills

Designs and verifies RTL (Register Transfer Level) logic for AI hardware accelerators using Verilog/VHDL and industry-standard EDA tools.

Open 25d APACFull-timeLead

RTL Micro Architect Lead