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Square One Resources

Logic Design Engineer (FPGA)

RemoteEurope Licensed UK sponsor

Designs FPGA digital logic for a client project: writing RTL in SystemVerilog and working with digital logic design, using tools like Vivado and VCS. Requires a B.Sc. in Electrical/Computer Engineering and 4+ years of professional experience. Remote-friendly role based in Warsaw, Poland.

FPGA Rtl SystemVerilog

Quantum Machines

Micro-Architect

Open 68d HybridMENA

Quantum Machines is hiring a Micro-Architect in Tel Aviv to define and implement the micro-architecture of advanced digital logic components for its quantum computing control systems, taking designs from concept through high-quality RTL. The role centers on RTL design, architectural trade-offs, and performance/area optimization.

Rtl SystemVerilog Verilog

Renesas Electronics

Senior Engineer, Design Verification (MCU)

Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off Define and drive IP‑level verification strategies, including test plans, coverage models,…

Agile AI Analytics Automation Bash +16 skills

Advanced Micro Devices, Inc

Senior ASIC Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

AI Asic Bash C++ Firmware +6 skills

NormalComputing

FPGA Platform Lead

Open 114d HybridNorth AmericaLead

Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across RTL, verification, and physical design to tape out custom ASICs.

Accessibility AI Automation CI/CD C++ +16 skills

SambaNova Systems

Principal RTL Design Engineer

Open 66d North AmericaFull-timePrincipal Licensed UK sponsor H-1B sponsor history

Designs and owns the RTL for AI accelerator blocks, from microarchitecture to tape-out, focusing on high-frequency datapaths and PPA trade-offs.

Agentic AI AI Automation Ethernet GPU +5 skills

180K – 255K $

Advanced Micro Devices, Inc

Silicon Design Engineer

Open 33d APACSenior

Senior silicon design engineer on AMD's I/O IP team, developing Verilog RTL for host controller IP supporting next-gen high-speed I/O technologies (up to 40 Gb/s, e.g. USB4/Thunderbolt). Day-to-day involves designing reusable, functionally correct IP blocks, solving complex technical problems, and mentoring junior engineers.

AI Automation Bash Corrective Action Perl +7 skills

Microchip Technology

Senior Technical Staff Engineer - Analog & Mixed Signal Design

APACStaff Ireland permit employer

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…

Automation Perl Python Rtl SystemVerilog +2 skills

CPU Microarchitecture and Design Intern

HybridEuropeInternshipIntern Ireland permit employer

Arm CPUs are everywhere, from the devices in your pocket to laptops, servers and increasingly AI and infrastructure systems! If you are interested in how those processors are designed and optimised at the…

Accessibility AI Asic C++ Linux +6 skills

Junior Design Verification Engineer, Amazon Leo

North AmericaFull-timeJunior

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role:…

Cmos MATLAB SystemVerilog Uvm Verilog

Design Verification Manager

North America H-1B sponsor history

Location: San Diego, CA or San Jose, CA - Hybrid (Friday Remote) Our Team: Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing,…

Automation CI/CD Firmware I2c Perl +7 skills

Solutions Intern - Systems Modeling (FPGA)

APACInternshipIntern

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…

AI Automation ChatGPT Cloud C++ +11 skills

Principal Analog Mixed-Signal Design Verification Engineer

EuropePrincipal

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…

Cadence Virtuoso Cmos MATLAB Python SystemVerilog +1 skills

Principal Analog Mixed-Signal IC Design Engineer

EuropePrincipal

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…

Cmos MATLAB Simulink SystemVerilog

Senior Analog Mixed-Signal Design Verification Engineer

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…

Cadence Virtuoso Cmos MATLAB Python SystemVerilog +1 skills

Principal RFIC-PLL Design Engineer

EuropePrincipal

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…

Cmos MATLAB SystemVerilog

Digital ASIC Design Engineer

Open 9d North AmericaFull-time H-1B sponsor history

Overview: Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful…

Business Development SystemVerilog Verilog VHDL

SambaNova Systems

Director of ASIC Design Verification

Open 66d North AmericaFull-time Licensed UK sponsor H-1B sponsor history

Lead pre-silicon verification for SambaNova’s AI chips, owning methodology, testbenches, and tape-out readiness, then debug first silicon in the lab.

Agentic AI AI Asic Ethernet FPGA +8 skills

270K – 340K $

Senior FPGA/Silicon Design Engineer

On-siteNorth AmericaFull-timeSenior

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…

Automation Azure Cloud Cmos Firmware +10 skills

Advanced Micro Devices, Inc

Design Verification Lead

North AmericaLead

Leads design verification of next-generation PCIe and CXL-based IP in AMD's AECG group, building UVM verification environments, running regressions, and driving automation for first-pass silicon success. Core technologies: SystemVerilog, Verilog, UVM, PCIe/CXL protocols, and Python/Perl scripting.

AI Automation Ethernet Firmware FPGA +7 skills