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This role involves verifying and analyzing complex full-chip gate-level custom memory designs, including DDR and LPDDR architectures. The engineer will utilize AI-based tools, automation frameworks, and simulation environments to accelerate verification cycles and improve debug efficiency.
NVIDIA is seeking interns for a 12-week digital circuit design program focused on hardware development for accelerated computing. Interns will work on projects involving circuit design, simulation, and optimization using tools like Verilog, Python, and industry-standard EDA software.
A 12-week full-time internship in Mixed-Signal Design at NVIDIA, where students contribute to hardware projects impacting industries like AI, robotics, and healthcare. Core focus: analog circuit design, simulation, and hardware testing.
NVIDIA is seeking interns for a 12-week hardware verification program to work on projects involving GPU and processor architecture, functional testing, and digital design. Interns will utilize tools like SystemVerilog, UVM, and various simulation environments to support hardware validation efforts.
NVIDIA is seeking Ph.D. students for hardware research internships focused on circuit design, ASIC/VLSI development, and electronic design automation (EDA). Interns will collaborate with research teams to develop prototypes and publish original research in areas like ML accelerators, memory design, and high-speed signaling.
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
NVIDIA offers 12-week hardware engineering internships for students pursuing degrees in electrical or computer engineering. Interns work on projects across system validation, hardware design, mechanical engineering, and silicon solutions using tools like Python, Verilog, and various CAD software.
This role is for an RTL Design Team Lead to manage a hardware team and contribute hands-on to the development of complex FPGA and ASIC IP for 5G and satellite communications. The position involves technical leadership, team mentoring, and optimizing hardware designs for performance and power efficiency.
This role involves leading the architecture and development of embedded firmware and FPGA logic for complex medical instrumentation platforms. The engineer will work with ARM-based SoCs, Linux BSPs, and high-speed data interfaces to optimize system performance in a laboratory environment.
Job Overview: Are you an RTL engineer eager to build expertise across multiple IP products? Do you want to work globally with internal teams to develop systems optimized for performance and power? If so, we want to…
Principal FPGA Design Engineer at Microchip's Chandler Design Center developing and validating FPGA-based platforms for next-gen USB and Ethernet PHY products using Verilog/SystemVerilog RTL design, Vivado, and lab debug equipment.
Designs and verifies FPGA logic for Microchip PolarFire SoCs using VHDL/Verilog, integrating with RISC-V cores and Linux/RTOS drivers.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
An intern designs ultra-low-latency FPGA systems for trading infrastructure, working with hardware design, RTL, and performance optimization alongside a small engineering team.
Develops GPU applications and emulation tools to verify AMD’s pre-silicon hardware for AI/ML and HPC workloads, focusing on debugging, benchmarking, and performance analysis.
Design and run C/C++ tests, firmware, and FPGA RTL for embedded SoC validation, debug silicon bring-up issues, and automate flows with Python.
Design Verification Engineer builds SystemVerilog/UVM test environments to verify AI chip control, initialization, and state transitions for SambaNova’s RDU chip.
Intern designs FPGA/ASIC hardware for ultra-low latency trading systems, coding in SystemVerilog/Python and bringing designs to life on real silicon.
Role Overview We are seeking a highly experienced Design Verification Leader to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI,…
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