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Lead Software Engineer at Cadence working on the Innovus Place & Route product, developing timing and power optimization for chip design using C/C++ in a Linux environment.
Design and verify digital integrated circuits using Verilog/SystemVerilog, collaborating with cross-functional teams to implement and optimize semiconductor solutions.
Designs and implements custom IP/SoC physical layouts from RTL to GDS, optimizing for timing, power, and manufacturability using FPGA/ASIC flows.
Обязанности: Разработка, тестирование, отладка и сопровождение в производстве блоков обработки радиолокационной информации. Требования: Опыт работы от 3 лет (контроллеры, разработка ПО для встраиваемых систем и систем…
Design and optimize standard cell libraries and flows for Apple’s custom processors using Verilog/SystemVerilog, EDA tools, and ML-driven analysis to improve timing, power, and area.
Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a…
B2C Senior Product Designer, AI Experiences 100% remote role Who worked with HP, Lenovo, Dell, Acer, ASUS, Apple, Microsoft, Samsung, LG, Sony, Huawei, Xiaomi, OnePlus, Oppo, Vivo, Motorola, Nokia, Google, Amazon,…
Designs and optimizes custom silicon solutions for Google’s hardware, focusing on physical design methodologies, timing/power closure, and SoC partitioning to enhance performance and efficiency in AI and infrastructure products.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
FPGA Design Engineer owning the design and implementation of FPGA-based interfaces (PCIe, I2C, SPI, high-speed GT) on Xilinx UltraScale+ and Versal platforms for quantum computing control systems.
Project description Looking for a Validation Engineer who can collaborate with teams and be available at the office every working day. Responsibilities * Own test planning, execution, coverage, reporting and defect…
This role involves translating system-level requirements into FPGA specifications and performing hands-on FPGA design, verification, and integration for mission-critical systems. The engineer will work with Xilinx or Intel platforms, manage system architecture, and collaborate with cross-functional teams to validate hardware and firmware interactions.
Relationship Manager Sales CEQ REPORTS TO (SOLID & MATRIX): Position Grade: Business Unit: SME Department: Sales Sub Function: CEQ Location: Number of Positions: Single / Multiple Position Type: Full Time Job…
Lead digital design for power-management ICs, defining architecture, RTL, synthesis, and timing while collaborating with global teams to deliver high-efficiency converters for consumer, industrial, and automotive applications.
The role involves validating and debugging USB host/device functionality, HPS boot flows, and peripheral integration for next-gen FPGA SoC devices, ensuring reliability and customer readiness through hands-on SoC bring-up, protocol validation, and advanced silicon debugging.
Graduate engineer validates next-gen FPGA SoC USB subsystems in lab, running tests, debugging silicon, and automating validation with Python/TCL.
Job Details: Job Description: Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip.…
Designs and develops advanced FPGA-based embedded systems and AI/ML algorithms for semiconductor equipment, focusing on heterogeneous processing architectures, IP core development, and troubleshooting complex hardware/software issues.
Develops and validates semiconductor PDKs, automates library workflows, and optimizes physical design for advanced chip manufacturing using Synopsys/Cadence tools.
An internship designing RTL for HBM SoC logic die, collaborating with architecture/verification teams to implement high-performance SoC solutions and integrating AI-driven tools into workflows.
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