Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
Leads RTL design for Google’s custom silicon solutions, focusing on ASIC development for SoC/VLSI, Verilog/SystemVerilog coding, and hardware-software integration to power Google Cloud and consumer products like Vertex AI.
What We’re Looking For: We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.…
Leads physical design flows for next-gen PCI/CXL/IDE controller IPs, focusing on timing closure, PPA optimization, and signoff using Synopsys tools.
Design and verify ASIC/SoC hardware using UVM, SystemVerilog, and Synopsys tools to catch silicon-critical bugs before tape-out.
Designs and optimizes ASIC physical layouts using Cadence/ Synopsys tools, closing timing and power while driving tapeout readiness in a fast-paced chip startup.
Software Engineer at Xenergic AB developing memory compiler flow, verification flow, and improving internal processes and IT setup. Core technologies include Python, Linux/Unix environment, Git, and EDA tool scripting.
Design AI/ML accelerator ASICs and storage solutions, defining I/O subsystems (PCIe/UCIe/CXL) and memory hierarchies for high-performance AI workloads.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/VHDL and ASIC flows.
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Designs and verifies integrated circuits for ASIC development, including architecture, logic design, and system simulation, with a focus on timing and power efficiency.
Principal Digital Design Engineer designing secure embedded controllers and cryptographic hardware for automotive, industrial, and defense markets using ASIC/FPGA flows, Verilog/VHDL, and security countermeasures.
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique…
Designs and verifies ASIC IP for Qualcomm’s Snapdragon DSP/NPU, using UVM and SystemVerilog to accelerate AI and video workloads in connected devices.
Implementation Timing / STA Design Engineer Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area: Engineering…
Staff Memory Controller Architecture and Design Engineer Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area:…
Lead a team to perform Static Timing Analysis (STA) on Google’s custom silicon SoCs, ensuring timing closure and low power for AI accelerators while collaborating with architecture and physical design teams.
Design and deploy power-efficient Network-on-Chip (NoC) interconnects for Qualcomm SoCs, focusing on power-performance optimization and low-power techniques across mobile, automotive, and IoT devices.
Video Codec Design Engineer, up to Staff Location: Taipei, Taipei City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group…
We couldn't check your fit for this role — add a CV to your profile to see it next time.