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Lead a team to verify Google’s TPU silicon, defining advanced verification flows and methodologies to ensure functional correctness and performance of AI hardware accelerators.
Develop and verify embedded firmware in C/C++ for mixed-signal power management ICs, collaborating with RTL teams to define hardware interfaces and ensure ROM-ready code.
Design and integrate RTL for mixed-signal power management IP, drive timing closure, and tape-out while collaborating with analog, firmware, and physical design teams.
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
Leads verification of complex SoC subsystems (e.g., memory/cache, coherency, PCIe/DDR) using UVM/SystemVerilog, ensuring functionality, performance, and security. Owns test strategy, debugging, and cross-team collaboration for sign-off.
Core Debug Engineer at AMD verifies next-gen microprocessor designs, collaborates with RTL engineers, and resolves complex logic bugs to ensure functionality and architectural compliance.
Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.
Builds and maintains hardware emulation models for SambaNova’s AI workload accelerator (RDU), enabling pre-silicon software bring-up, performance verification, and verification acceleration. Works with RTL teams to ensure emulation-readiness, owns platform automation, and advises cross-functional teams on emulation strategy.
Design and verify custom silicon accelerators and SoCs for Google’s AI and hardware infrastructure using SystemVerilog, UVM, and formal methods.
Design and execute verification plans for a Physical AI SoC using SystemVerilog/UVM, C/C++, assertions, and emulation to validate compute engines, memory, and interconnects.
Configure and integrate RISC processor IP into SoC platforms, customize processor features, develop RTL wrappers and system glue logic, integrate interconnects and interrupt controllers, support verification and system…
Integrate commercial RISC-V core soft IP with external accelerators, tailor CPU features to meet performance, power, and area requirements, modify Verilog and SystemVerilog RTL, collaborate across ASIC design…
Join Bitdeer's IC development team to ensure the functional correctness and performance of computer arithmetic IPs. Develop comprehensive verification environments, execute test plans, debug RTL issues, and…
Leads ASIC/SoC design and verification for high-performance GPU/graphics workloads, architecting power-efficient digital/analog blocks from concept to deployment.
Designs and implements RTL for SoC PAD/PFC logic (pin multiplexing, I/O control) using Verilog/SystemVerilog, in-house tools, and automation scripts to ensure design quality and integration.
Lead a team to architect and execute advanced verification strategies for next-gen semiconductor products using SystemVerilog, UVM, and emulation platforms.
Design/Verification Engineer applying AIML-enhanced methodologies to architect UVM testbenches, drive coverage closure, and automate RTL generation for complex digital ASIC/SoC designs from RTL to tapeout.
Senior Design Verification Engineer at HPE focused on emulation-based verification of complex digital designs, building UVM/SystemVerilog testbenches and running designs on platforms like Palladium, ZeBu, and Veloce.
The Firmware Lead will develop and implement FPGA-based firmware for high-performance motion control systems, utilizing VHDL, Verilog, and SystemVerilog. The role involves designing control algorithms, managing industrial communication protocols, and mentoring junior engineers in a safety-compliant environment.
The Software Engineer II will develop and validate CXL Verification IP, collaborating with global teams to create robust software solutions for hardware and SoC memory protocol verification. The role requires strong C/C++ modeling skills and experience with verification methodologies.
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