Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Senior Staff Test Engineer develops, characterizes, and validates analog/digital test modules for ASIC production (wafer and final test), collaborating with VLSI teams to define ATE test specs, design hardware (load boards/probe cards), and ensure high-speed SerDes testing quality for Qualcomm’s semiconductor products.
Senior Physical Design Engineer at Qualcomm leading floorplanning, placement, and timing closure for high-speed digital blocks on advanced nodes (TSMC N5/N4P/N3) using Synopsys ICC2, Cadence Innovus, and AI-assisted EDA flows.
Designs and optimizes CPU physical layouts using Place & Route tools (FC/Innovus), STA (Primetime/Tempus), and UPF/CPF for low-power, high-speed ASICs.
Designs and validates RTL for DDR memory interfaces and low-power SoCs, ensuring timing closure and compliance with AHB/AXI protocols.
Lead a team designing custom silicon and SoCs for Google’s AI and cloud infrastructure, overseeing RTL coding, simulations, and physical design to deliver high-performance hardware.
Designs high-performance PCIe Gen6/Gen7 switch ASIC IP using SystemVerilog, focusing on RTL implementation, timing closure, and architecture for next-gen connectivity solutions.
Design next-gen Ethernet ASICs for AI/HPC networks, writing micro-arch specs, closing timing, and verifying RTL blocks to optimize silicon performance.
Senior Architect defines next-gen chip interconnects like NVLink, optimizing performance and power while driving ASIC design and cross-team implementation.
A Product Test Engineer at Cisco develops and manages test solutions for advanced networking silicon, ensuring production targets are met by resolving hardware/software issues, optimizing yield, and collaborating with OSATs and engineering teams.
Leads functional-safety activities for RISC-V-based semiconductor IP, ensuring ISO 26262 compliance across the full product lifecycle and collaborating with hardware, software, and verification teams.
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the…
Lead a team designing and automating Design-for-Test (DFT) features for complex ASICs, GPUs, and APUs using Perl, Python, TCL, and AI/ML tools.
Design Verification Engineer at AMD builds and maintains tests to verify complex processor IP, debug failures, and collaborate with RTL and firmware teams to ensure high-quality silicon designs.
Designs and implements DFT/DFD features for AMD’s ASICs (APUs, GPUs, game consoles) while automating workflows via Python/Perl/TCL scripts and debugging CAD/IP regressions.
Lead FPGA and ASIC design, integration, and validation for high-performance computing IPs, mentoring junior engineers and shaping technical direction in a hybrid role.
SOC Architect Team: Technology, Information and Media Location: Bengaluru Commitment: Full-time Workplace Type: onsite Salary: We are looking for an experienced and highly motivated Lead SoC Architect to lead the…
Role Overview We are looking for a Director of ASIC Design to drive the design, development, verification, and execution of high-performance AI inference chips. This role requires deep technical expertise in ASIC…
Build a compiler-like design automation pipeline that turns high-level building plans into manufacturable models and production plans for Reframe’s climate-resilient microfactory homes.
Hardware Engineer, Physical Design Department: Engineering Location: New York City, London, Zurich, Silicon Valley, Copenhagen Compensation: $200K – $400K • Offers Equity Employment Type: FullTime About Normal…
Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
