Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Leads verification strategy for next-gen semiconductor interconnect products, building UVM/SystemVerilog testbenches and driving silicon success for high-speed digital designs.
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
Designs and implements CPU micro-architectures and RTL for high-performance, low-power chips, collaborating with architects and verification teams.
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Lead RTL design for audio hardware at Qualcomm, optimizing circuits and collaborating with cross-functional teams to deliver cutting-edge chipsets for mobile and embedded systems.
Senior ASIC Implementation Engineer, Low Power AI Location: Markham, Ontario, Canada Department: ASICS Engineering Work Location: onsite Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group >…
DSP Systems Engineer, Staff Location: Toronto, Ontario, Canada Department: Systems Engineering Work Location: onsite Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > Systems Engineering…
Design and optimize timing constraints for Qualcomm’s Oryon CPU cores using industry tools like PrimeTime and Tempus, scripting in TCL/Python, and collaborating with RTL and implementation teams.
Design and implement CPU microarchitecture and RTL for high-performance, low-power devices, collaborating with architects and verification teams.
Own the end-to-end SoC program for a next-gen Physical AI chip, coordinating silicon, platform, software, and vendor teams from architecture through tapeout and bring-up.
Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled team developing cutting-edge silicon for GenAI workloads, where we push the…
Electronics Design Engineer Location: Princeton, NJ, US Employment Type: FULL_TIME Overview SRI’s Integrated Systems & Solutions Division designs leading-edge R&D technologies that power the systems end users…
Design and verify FPGA-based prototypes for Intel’s IP blocks, integrating and debugging RTL designs to enable early hardware and software validation.
Develop and maintain hardware emulation platforms for ASIC/SoC designs, integrating and debugging RTL in emulation environments to enable pre-silicon validation.
Design AI inference systems and memory architectures, optimizing performance, power, and bandwidth for AI/ML workloads while collaborating with hardware and software teams.
Lead a team to implement and tape out high-performance ASIC/APU/dGPU designs for AI, gaming consoles, and automotive using RTL-to-GDS flows, PnR, timing closure, and physical verification.
Verify and validate AMD’s next-gen GPU and SoC designs using SystemVerilog/UVM, emulation platforms, and formal methods to ensure silicon meets performance, power, and functional specs.
Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Designs and verifies GPU and control subsystems for AI-focused SoCs, integrating Arm IP and third-party components for edge, physical, and cloud AI applications.
Designs and optimizes FPGA/ASIC hardware for low-latency trading systems using SystemVerilog, RTL, and vendor tool suites.
We couldn't check your fit for this role — add a CV to your profile to see it next time.