Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Designs and runs RTL validation for Intel’s IP blocks, using System Verilog and UVM to verify DDR5/LPDDR5 and debug failures before tape-out.
Builds and maintains real-time financial market data pipelines, ensuring accuracy, low-latency distribution, and integration with exchanges/vendors. Core tech: FIX/TREP protocols, cloud (AWS/GCP), scripting (Python/Bash), and network optimization.
The Semiconductor Design Engineer designs and analyzes digital and analog circuits for memory products, managing layout, verification, and simulation processes. The role involves collaborating with cross-functional teams to optimize manufacturing and ensure product quality using tools like Cadence Virtuoso, SPICE, and various hardware description languages.
NVIDIA is seeking interns for a 12-week hardware verification program to work on projects involving GPU and processor architecture, functional testing, and digital design. Interns will utilize tools like SystemVerilog, UVM, and various simulation environments to support hardware validation efforts.
NVIDIA is seeking interns for 12-week roles in hardware physical design and VLSI, focusing on chip implementation, timing closure, and physical verification using industry-standard EDA tools. Interns will work on projects impacting accelerated computing, AI, and robotics while pursuing their degree.
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
NVIDIA is seeking M.S. or Ph.D. students for a 12-week Hardware Design for Test (DFT) internship. Interns will work on hardware testing architectures, digital design, and silicon debug using tools like Synopsys and Cadence.
NVIDIA offers 12-week hardware engineering internships for students pursuing degrees in electrical or computer engineering. Interns work on projects across system validation, hardware design, mechanical engineering, and silicon solutions using tools like Python, Verilog, and various CAD software.
ASIC Physical Design Methodology Engineer defining and optimizing RTL2GDS flows and CAD methodologies for custom ML accelerator chips (Inferentia, Trainium) at Amazon's Annapurna Labs, using TCL and Python to build scalable design flows.
Principal FPGA Design Engineer at Microchip's Chandler Design Center developing and validating FPGA-based platforms for next-gen USB and Ethernet PHY products using Verilog/SystemVerilog RTL design, Vivado, and lab debug equipment.
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before…
We are seeking an experienced Sr. Staff QA Engineer to drive quality for our GigaSMART AppIntel features. In this role, you will define test strategies, lead complex validation efforts, and build robust automation to…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
About the Role We are seeking an experienced System Validation Engineer to join a team responsible for the integration, bring-up, and validation of next-generation System-on-Chip (SoC) products used in data center,…
Develops GPU applications and emulation tools to verify AMD’s pre-silicon hardware for AI/ML and HPC workloads, focusing on debugging, benchmarking, and performance analysis.
Design Verification Engineer builds SystemVerilog/UVM test environments to verify AI chip control, initialization, and state transitions for SambaNova’s RDU chip.
We are seeking a Senior Analog Layout Design Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the…
We are seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of…
We couldn't check your fit for this role — add a CV to your profile to see it next time.
