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Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.
Design and verify custom silicon chips for next-generation data storage hardware, using RTL, Verilog/SystemVerilog, and digital logic while collaborating with cross-functional engineering teams.
Design and verify custom silicon and hardware for next-generation data storage devices, collaborating across ASIC, firmware, and systems engineering teams using RTL, Verilog, and embedded C/C++.
Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
Lead FPGA design and architecture for defense electronics using VHDL, targeting Xilinx/Altera/Microsemi devices, and verify with constrained-random testing.
Designs and validates high-speed optical communication chips, writing RTL, running simulations, and debugging silicon to meet power and performance targets.
Manage GPU hardware development programs from IP to commercialization, coordinating cross-functional teams to deliver mobile GPUs with features like ray tracing for Samsung Galaxy devices.
Analog & Mixed-Signal ASIC Design Engineer At Tektronix, we believe innovation starts with our customer. This approach has led us to a seventy-five-year history of delivering outstanding solutions to customers in…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
Designs and integrates hardware components into Apple’s next-gen SoC, writing and merging RTL code, managing IP blocks, and ensuring timing closure with industry-standard tools.
Designs and verifies custom silicon for Google's TPU AI accelerators, focusing on SoC-level RTL, architecture, and integration within AI/ML systems.
Design and integrate custom TPU silicon for AI/ML workloads, owning multi-chiplet SoC architecture, interposer planning, and RTL integration to deliver high-performance hardware at scale.
Senior engineer designs and optimizes ASIC chip logic using synthesis and static timing tools, collaborating with cross-functional teams in a fast-paced hardware development environment.
High Speed IP PHY Applications Principal Engineer / Manager Location: Yongin-Si, Korea, Republic of We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate…
Sr. Staff Project Engineering Manager (High Performance Computing Serdes PHY)- 16938 Location: Noida, India We Are: At Synopsys, we drive innovations that shape how we live and connect. Our technology powers chip…
Program Engineering Management, Staff Engineer Location: Moreira Da Maia, Portugal We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive…
Front-End & Back-End SoC Engineering, Principal Engineer Location: Munich, Germany We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
PCIE SOC Application Engineer (Sr Staff) Location: Dublin, Ireland We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence,…
Principal Product Manager - Memory Interfaces Location: US (non-CA) Off-Site, US (non-CA) Off-Site Office, United States We Are: Synopsys is the leader in engineering solutions from silicon to systems, enabling…
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