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Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Designs and verifies GPU and control subsystems for AI-focused SoCs, integrating Arm IP and third-party components for edge, physical, and cloud AI applications.
Designs and optimizes FPGA/ASIC hardware for low-latency trading systems using SystemVerilog, RTL, and vendor tool suites.
Design Verification Engineer at Cerebras, building and testing the world's largest AI chip to ensure first-silicon success and ultra-fast AI inference.
Lead the design of Cerebras' next-generation AI chips, focusing on high-performance RTL development and integration while collaborating with cross-functional teams and external ASIC vendors.
Lead a team designing next-generation HBM SoC logic dies for AI/ML, driving architecture, RTL implementation, and integration while optimizing performance, power, and area.
Design and optimize DRAM RTL blocks using AI-driven tools, then integrate and verify them through full-chip flows including CDC, synthesis, and STA.
Design and verify next-gen memory chips, from full-chip functional checks to mixed-signal circuits and array architecture, using SystemVerilog, SPICE, and Cadence tools.
Principal RTL Design Engineer at Micron leads DRAM digital and mixed-signal IP development, owning RTL design from architecture to silicon-ready signoff while optimizing power, performance, and area.
Design and run verification testbenches for DRAM memory blocks using SystemVerilog/UVM, analyze coverage, and debug failures to ensure tapeout readiness.
Design and implement GPU micro-architecture in RTL using Verilog/VHDL, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Senior Manager, ASIC Chip Engineering Location: US, CA, Santa Clara Time Type: Full time Job Description NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of…
Build AI-assisted tools to improve RTL, verification, and debug workflows for hardware engineers, turning AI models into practical engineering solutions.
Lead end-to-end SoC development from architecture to commercialization, managing cross-functional teams and driving hardware-software co-design for complex semiconductor products.
Designs and verifies RTL for AI-focused ASIC/SoC chips, integrating IP blocks and optimizing power, performance, and area for tapeout.
Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping…
Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.
Principal Design Engineer- Emulation (m/w/d) Location: Germany - Karlsruhe Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member…
Designs and verifies custom silicon for Google’s TPU accelerators, focusing on microarchitecture and on-chip networks that power AI workloads at hyperscale.
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