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Build and maintain hybrid-cloud and on-premises infrastructure for D-Wave’s quantum computing services, automating deployments and CI/CD pipelines while ensuring high availability and security.
Design and integrate RTL for mixed-signal power management IP, drive timing closure, and tape-out while collaborating with analog, firmware, and physical design teams.
The Data/BI Analyst extracts, transforms, and loads data (ETL) from various sources using SQL, optimizes databases for business needs, analyzes customer data, and creates dashboards/reports to drive insights and automate processes in a fintech payment system.
Develops and maintains emulation infrastructure for Google Cloud’s TPU hardware, focusing on verifying complex digital designs and debugging emulation platforms to accelerate AI/ML hardware acceleration.
The role develops and integrates PCIe-related IP blocks, evaluates performance, supports verification closure and functional coverage, debugs pre-silicon and post-silicon issues, and contributes to software development…
Integrate commercial RISC-V core soft IP with external accelerators, tailor CPU features to meet performance, power, and area requirements, modify Verilog and SystemVerilog RTL, collaborate across ASIC design…
Data Analyst/DWH Analyst at NovaPay (fintech) handles ETL, database optimization, client analysis, and dashboard creation using SQL (PostgreSQL/MS SQL/Oracle), Excel, and Power BI.
Lead digital ASIC design and ATPG for automotive semiconductors, defining test strategies and improving product quality through scripting and cross-team coordination.
Lead physical design (RTL-to-GDS) for AMD’s next-gen AI and high-performance ASICs, driving PnR, timing closure, and tape-outs while collaborating with architects and EDA vendors.
Designs and implements RTL for SoC PAD/PFC logic (pin multiplexing, I/O control) using Verilog/SystemVerilog, in-house tools, and automation scripts to ensure design quality and integration.
Senior ASIC verification engineerThis role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company…
Design/Verification Engineer applying AIML-enhanced methodologies to architect UVM testbenches, drive coverage closure, and automate RTL generation for complex digital ASIC/SoC designs from RTL to tapeout.
Senior Design Verification Engineer at HPE focused on emulation-based verification of complex digital designs, building UVM/SystemVerilog testbenches and running designs on platforms like Palladium, ZeBu, and Veloce.
Digital Design Engineer on a 12-month contract managing IP/RTL design and verification for a global semiconductor company, using VHDL/Verilog, scripting languages, and communication IPs.
Key Objective of the Job: As Sales Manager, you are responsible to lead generation, good interpersonal skill, good communication skills, Liaison with other function, dealership management, assist CSEs for their daily…
Main Accountabilities Create and manage data flow diagrams to track personal data across systems. Prepare and update Records of Processing Activities (RoPA) in line with regulatory requirements. Work on Project for…
Develop and deploy software solutions that enhance CPU design tool capabilities, maintain an internal HPC cloud infrastructure, and help build an AI-assisted development environment within Intel's All Cores Engineering organization.
Job Summary: ASSET InterTech creates software (ScanWorks BST) that tests hardware. We are seeking a Senior Applications Engineer with deep expertise in both hardware and software to lead technical support initiatives…
Develop physical design, STA, and power integrity flows and methodologies for NVIDIA's high-speed networking chips and SOCs, working with tools like PrimeTime and PrimePower.
Alternate Job Titles Physical Design Lead ASIC Physical Design Manager Backend Design Manager Place and Route Manager Physical Implementation Manager We Are Synopsys is the leader in engineering solutions from silicon…
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