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Designs and verifies analog and mixed-signal integrated circuits for power systems, from concept to post-layout, using Cadence tools and collaborating across teams.
Lead the design and delivery of high-speed ASICs for optical data transmission, overseeing chip architecture through mass production and global team coordination.
Principal Engineer in Marvell’s Design Verification team, building and running testbenches to verify high-speed storage IP like read channels and cryptographic engines using SystemVerilog/UVM and EDA tools.
Design verification engineer building and running testbenches for high-speed storage IP (HDD/SSD) using SystemVerilog/UVM and collaborating with SoC teams to debug complex digital designs.
Designs and automates AI/ML-driven chip design flows to optimize power, performance, and area for NXP’s SoCs and processors using Python/C++ and advanced ML techniques.
ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This approach has led us to a seventy-five-year history of delivering outstanding solutions to customers in virtually every…
Sr Staff - Physical Implementation Flow (experience - 8+ Years) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from…
An electrical engineer designs and evaluates analog, digital, mixed-signal, power, and RF circuits while reviewing AI-generated technical responses for accuracy to train next-generation AI systems.
Designs and automates test and debug features for complex AMD processors using scripting and AI/ML, ensuring scalable ASIC design flows.
- Bachelor's degree in Electrical Engineering or a related field - Knowledge of UVM and Matlab - Experience developing products for volume production - Experience low power design techniques - Master's degree…
Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.
Lead ASIC verification for Google Cloud hardware, owning outcomes, decisions, and stakeholder alignment using SystemVerilog and UVM.
Senior Principal FPGA Verification Engineer - $30K Sign On Bonus Location: Westminster, Colorado, United States Category: Engineering & Technology Employment Type: Full-Time Job Description Minimum $30,000 Sign On…
Principal Engineer SOC/ASIC Design Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area: Engineering Group,…
EM Design Engineer Location: Santa Clara, California, United States of America Department: RFIC Design Work Location: onsite Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > RFIC…
ASIC Chief Architect - Hod HaSharon Location: Hod Hasharon, Haifa District, Israel Department: Modem Technologies Work Location: onsite Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group >…
Lead Engineer/ Staff – RISCV Subsystem RTL Design Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
Security RTL Design Engineer-Sr Lead/Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Senior IP Micro-architect (RTL) - Staff/Sr Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
RTL Design - Sr Lead Engineer Location: Noida, Uttar Pradesh, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
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