Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Designs and verifies custom silicon for Google’s TPU accelerators, focusing on microarchitecture and on-chip networks that power AI workloads at hyperscale.
Design and implement high-performance FPGA logic for next-gen NAND Flash storage systems using Xilinx tools and RTL, while collaborating on embedded firmware and system validation.
The Apple design team is looking for an experienced engineer to develop multiple IPs for Apple SoCs (in Storage, Computer Vision and RISC-V CPU domains). In this Role you will get to handle micro-architecture…
Designs and verifies RTL IP blocks for networking solutions, collaborating with architects and physical design teams to ensure first-pass silicon success.
Verify and validate AMD’s next-gen GPU and SOC designs using Verilog/SystemVerilog, UVM, and emulation platforms like Veloce/Zebu to ensure functional correctness and performance.
Design and implement high-performance RISC-V CPU cores, focusing on microarchitecture, RTL coding, and collaboration with verification and physical implementation teams.
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Designs and drives the security architecture for FPGA, SoC, and ASIC products, focusing on hardware security, Root of Trust, secure boot, and cryptography to ensure resilient, compliant silicon solutions.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More…
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
Join Kyocera International, Inc. We’re hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education,…
Design and implement FPGA/ASIC applications using OCaml/Hardcaml, Verilog, and C, focusing on high-level tools for hardware development and testing.
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
Senior FPGA Engineer, Cyber Location: Washington, District of Columbia, United States Department: AFS : Discovery Engineering : Cyber Anduril Industries is a defense technology company with a mission to transform U.S.…
Develop and verify low-level Linux drivers and test plans for x86 CPU features, collaborating with hardware and firmware teams to debug and improve system performance.
Design and verify custom silicon for Google’s devices, building UVM testbenches and formal verification flows to ensure ASICs meet performance and reliability targets for AI and image-processing hardware.
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Integrate RISC processors (RISC-V/Arm) into SoC platforms, configure subsystems, and collaborate on RTL, firmware, and system bring-up for Bitdeer’s Bitcoin mining and AI cloud hardware.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
