Tech jobs

Atlassian Automation C++ C# Ethernet +15 skills

Senior FPGA Engineer

HybridSenior

The group you’ll be a part of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lam’s etch and deposition products. We drive innovation to ensure our cutting-edge solutions…

jobs.hii-tsd.com

Open 9d North AmericaFull-time

Digital Design Engineer

AI Assembly Bash Big Data C++ +11 skills

Requisition Number: 29344 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Anticipated Salary Range: $72,497.00 - $246,509.00 Security Clearance: Ability to Obtain Level of Experience: Mid This…

career.karlstorz.com

AI Embedded Software FPGA GPU Image Processing +5 skills

FPGA Engineer IV

About the Role At KARL STORZ, the FPGA Design Engineer IV is responsible for designing, developing, testing, integrating, and verifying FPGA-based and accelerated imaging solutions for advanced medical video camera…

Kyocera

Open 25d North AmericaPrincipal

Senior Principal Engineer, RFIC Design

Cadence Virtuoso Cmos EVM Firmware MATLAB +6 skills

Kyocera is hiring a Senior Principal Engineer in San Diego to lead end-to-end design of mmWave RFICs — owning the Tx signal chain (mixers, LO distribution, PAs, beamforming, calibration) for 5G FR2/FR3 and FMCW/pulse radar, from architecture and Cadence-based circuit design through verification, lab characterization, and production ramp, while mentoring engineers.

155K – 348K $

Kyocera

Open 25d North AmericaSenior

Senior RFIC Design Engineer

Cadence Virtuoso Cmos Design for Manufacturing (DFM) Firmware MATLAB +4 skills

Kyocera is hiring a Senior RFIC Design Engineer in San Diego to design and verify high-performance RF, analog, and mixed-signal integrated circuits for wireless and sensing products — from architecture and transistor-level design through layout, simulation, silicon characterization, and production ramp — using tools like Cadence Virtuoso and Spectre.

106K – 213K $

Arista Networks

Open 15d HybridNorth America Licensed UK sponsor Canada LMIA employer Ireland permit employer

FPGA Design Engineer

AI Arista Automation Bash Ethernet +11 skills

Designs and verifies control-path FPGA RTL (Verilog/SystemVerilog) for Arista's data center Ethernet switch platforms, owning the full lifecycle from architecture and board review through synthesis, timing closure, verification, and lab bring-up in collaboration with hardware, software, and manufacturing teams.

Arista Networks

Open 15d HybridNorth America Licensed UK sponsor Canada LMIA employer Ireland permit employer

FPGA Design Engineer

AI Arista Automation Bash Ethernet +11 skills

Design and verify high-performance control-path FPGAs for Arista's data center Ethernet switch platforms, owning the full lifecycle from Verilog/SystemVerilog RTL development and verification through synthesis, timing closure, and system bring-up. On-site role in Santa Clara, CA requiring 5+ years of RTL design experience.

110K – 170K $

Open 15d North AmericaSenior

Senior ASIC RTL Design Engineer, AI Networking IP

Senior ASIC RTL design engineer on AMD's IP team building high-performance networking and communications IP cores for AMD chips. Day to day: write synthesizable Verilog/SystemVerilog RTL, leverage AI coding tools for productivity, support synthesis/timing closure, verification regressions, and emulation, and mentor junior designers.

AI Asic Atlassian Bash ChatGPT +14 skills

Open 15d North AmericaPrincipal

Memory PHY Principal Design Engineer

AI Firmware Perl Python Rtl +4 skills

Seasoned engineer to architect and develop high-speed memory interface IP (LPDDR/DDR) at AMD — defining digital PHY architecture and microarchitecture, leading RTL implementation and firmware integration, and guiding synthesis, timing closure, and power optimization through silicon. Core tech: Verilog/SystemVerilog, UPF, Python/Perl/Tcl.

Open 15d North AmericaStaff

Senior Staff Product Application Engineer-Memory Subsystems

AI Automation Firmware JTAG LLM +8 skills

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

SambaNova Systems

Open 67d North AmericaFull-time Licensed UK sponsor H-1B sponsor history

Design Verification Engineer

Agentic AI AI Bash Firmware GPU +6 skills

Design Verification Engineer builds SystemVerilog/UVM test environments to verify AI chip control, initialization, and state transitions for SambaNova’s RDU chip.

120K – 200K $

SambaNova Systems

Open 67d North AmericaFull-timeSenior Licensed UK sponsor H-1B sponsor history

Senior Hardware Design Engineer

Agentic AI AI Asic Automation Bash +11 skills

Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.

120K – 200K $

MDA Space

Accessibility Asic Confluence Embedded Software FPGA +8 skills

FPGA Designer

Open 64d North America

Building the space between proven and possible, MDA Space is a trusted mission partner to the global space industry. A robotics, satellite systems and geointelligence pioneer with a 55-year+ story of world firsts and…

AI Machine Learning PCIe SystemVerilog Uvm +2 skills

IOHUB Design Verification Engineer

Open 15d North America

Design Verification Engineer on AMD's NBIO team, defining and executing verification for the IOHUB Core (PCI host bridge) and IOMMU IP blocks. Day to day: writing test plans and UVM/SystemVerilog components, and driving coverage-based verification closure for interconnect IP used in GPUs, APUs, servers, and game consoles.

AI Analytics Asic Automation Bash +13 skills

Staff Design Verification Engineer

Open 75d UKStaff

United Kingdom

Design verification engineer at AMD, building and automating testbenches to verify next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.

AI Analytics Asic Automation Bash +11 skills

Staff Silicon Design Verification Engineer

Open 43d UKStaff

United Kingdom

Senior design verification engineer on AMD's networking silicon team in Edinburgh, verifying next-generation network processors and SmartNICs. Day-to-day involves building UVM/SystemVerilog testbenches, developing directed and constrained-random tests, debugging RTL/firmware, driving coverage closure, and improving productivity through scripting, automation, and AI-assisted workflows.

Google

Open 15d APACLead Licensed UK sponsor Licensed NL sponsor Denmark Fast-track company

Silicon SoC Integration Design Lead, Google Cloud

India

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

Asic Firmware SystemVerilog Verilog VHDL

Agentic AI AI Cloud FPGA Go-to-Market +7 skills

Technical Marketing Engineer – FPGA Design

Open 80d UK

United Kingdom

Technical Marketing Engineer creating training, documentation, and demos for AMD’s Vivado FPGA tool suite, validating features and enabling customers through clear technical communication.