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DSP / NPU Staff Design Verification Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
RTL Design (Infra/NOC/SMMU/DDR/Peripherals) Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Staff/Senior Staff Physical Design Engineer Location: Ho Chi Minh, Hồ Chí Minh, Vietnam Department: ASICS Engineering Work Location: onsite Company: Qualcomm Vietnam Company Limited Job Area: Engineering Group,…
Lead the architecture and integration of a custom high-performance edge SoC for a stealth startup, defining system blueprints and guiding a Tier-1 ASIC partner through implementation.
Lead the design of a next-generation edge SoC for a stealth startup, defining microarchitecture, driving PPA tradeoffs, and integrating high-performance IP to power a custom computing platform.
Designs and implements ASIC physical layouts for Cisco’s advanced networking chips, using RTL-to-GDS flows, place-and-route, and timing closure in a collaborative VLSI team.
Engineer regulatory compliance for Cisco’s wireless and networking hardware, defining EMC/RF requirements, running pre-compliance tests, and guiding design fixes to meet global certifications like FCC, CE, and RED.
Senior engineer verifying FPGA-based designs for NVIDIA’s Holoscan edge-compute platform, using SystemVerilog/UVM and collaborating with architecture teams to validate real-time AI and connectivity features.
Develop and optimize AI-driven video analytics algorithms for embedded Linux systems, collaborating with hardware teams to implement production-ready deep learning models and ASIC designs.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Design and verify ASICs for HP printers, leading RTL coding, verification, and silicon validation while collaborating with cross-functional teams to deliver embedded solutions.
Designs and implements automated test and debug features for AMD's complex processor and GPU chips, using scripting and AI/ML tools to improve chip reliability and performance.
Designs and integrates high-performance, low-power pixel processing ASICs for Apple’s SoCs, collaborating across teams to deliver functional multimedia IP for millions of devices.
About the Business Unit: Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer. Our advanced wireless…
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on control subsystems and SoC integration within AI/ML-driven systems.
Technical Director PCIe Controller Architect Location: San Jose, CA, US, Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PCIe…
SPE Hardware Architecture Location: San Jose, CA, US, Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Memory Controller Architect and…
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
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