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Great opportunity for an experienced ASIC Architect to join an innovative next- computing company and taking ownership of the architecture and development of a cutting-edge probabilistic computing processor. This is a…
Job DescriptionJob Description Job Title: Senior FPGA Engineer Department: Engineering Reports To: Functional Team Lead / Program Manager FLSA Status: Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are…
Senior FPGA Engineer | £(Apply online only)k (Dependant on experience) | Cambridge This is an opportunity to join a global team developing ultra-low latency technology. You will oversee all aspects of FPGA system…
Senior FPGA Design Engineer | Hybrid | Cambridge Join an innovative technology company developing advanced electronic products used in demanding, high-performance applications. You'll become part of a collaborative…
AMD is hiring a Tile Place & Route (PnR) Lead in Markham, ON to own physical implementation of complex SoC tiles from floorplan through tapeout at advanced process nodes — driving strategy, schedule, design quality, and mentoring engineers. Core work spans floorplanning, placement, CTS, routing, timing/IR-EM closure, and flows like ICC2, Fusion Compiler, PrimeTime, RedHawk/Totem, and Calibre.
Leads the full lifecycle of next-generation UALink switching chips for AI infrastructure, overseeing architecture, design, validation, and tapeout while aligning cross-functional teams in San Jose or Israel.
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads the design and implementation of high-performance digital IPs and SoC subsystems for AI infrastructure connectivity chips using Verilog/SystemVerilog, CXL, PCIe, and Ethernet.
Principal Digital Design Engineer at Astera Labs in Taipei will architect and implement complex digital blocks for high-performance AI connectivity silicon, owning designs from micro-architecture through silicon bring-up. Core technologies: RTL design, Cadence/Synopsys flows, PCIe/Ethernet/DDR protocols, timing closure, DFT, and UVM verification.
Senior digital design engineer at Astera Labs owning complex digital blocks for AI connectivity silicon — from micro-architecture and RTL implementation through timing closure, DFT, verification support, and silicon bring-up — targeting PCIe Gen 6/7, CXL, UALink, Ethernet, and DDR protocols on sub-7nm nodes using Cadence/Synopsys flows.
Architects and implements complex digital blocks for Astera Labs' AI connectivity silicon, owning designs from micro-architecture and RTL through timing closure, DFT, verification, and post-silicon bring-up for protocols like PCIe Gen 6/7, CXL, UALink, UCIe, Ethernet, and DDR, using Cadence/Synopsys flows on advanced CMOS nodes.
Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable…
AMD's Cores team in Fort Collins, CO seeks a senior RTL design engineer to design high-performance, energy-efficient cache and routing-fabric microarchitecture for next-generation CPU cores, collaborating with architecture, physical design, verification, and DFT teams. Key tech: digital RTL design, Verilog, and cache/coherency architecture.
Renesas is a global semiconductor company providing hardware and software solutions for various cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications.…
Quantum Source is hiring a Senior FPGA Team Leader in Rehovot, Israel to lead FPGA and electronics development for a photon-atom quantum computer. The role is hands-on: owning FPGA architecture and RTL, PCB lifecycle from schematic to bring-up, and system integration using Verilog/VHDL, FPGAs, and board-level electronics.
The Memory Technology Group is at the core of Sandisk's engineering organization. We are building a cutting edge 3D memory in our multi-billion dollars lab. Our memory provides performance, power, and endurance at…
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