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Principal Design Engineer at Rambus to architect and implement next-gen PCIe IP in System Verilog, prototype on FPGAs, and collaborate with global teams.
Oversee semiconductor IC design quality, certifications, and supply-chain quality for a chip-development firm, driving ISO 9001 compliance and defect reduction across the full lifecycle.
Designs and verifies digital sub-circuits for high-performance micro-controllers using Verilog/SystemVerilog, synthesis, and formal verification, collaborating with analog and software teams.
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Principal engineer designing and verifying PCIe/CXL IP subsystems in SystemVerilog for Marvell’s custom SoCs powering hyperscale cloud and AI data centers.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Design and implement FPGA firmware for next-gen radar and sensing systems, integrating with software and hardware for defense and commercial applications.
Design and implement FPGA-based digital signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused product company.
Design and implement FPGA-based signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused R&D environment.
Leads RTL design for Google’s custom silicon solutions, focusing on ASIC development for SoC/VLSI, Verilog/SystemVerilog coding, and hardware-software integration to power Google Cloud and consumer products like Vertex AI.
Logic Design Engineer Location: Israel - Haifa (IL) Description Chips Talk, We Listen proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital…
Lead the RTL design and microarchitecture of an ultra-low-power SoC for edge AI/IoT, defining dataflow fabrics, memory subsystems, and interconnects using SystemVerilog and collaborating across hardware, firmware, and verification teams.
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on high-performance RTL code and cross-functional integration with verification and physical design teams.
Software Engineer at Xenergic AB developing memory compiler flow, verification flow, and improving internal processes and IT setup. Core technologies include Python, Linux/Unix environment, Git, and EDA tool scripting.
With our groundbreaking satellite 5G constellation, OQ Technology is a global leader in IoT communication connectivity and associated services. We are a venture capital-backed company with a successful track record of…
Designs AI inference systems and memory architectures, optimizing performance, power, and scalability while co-designing hardware and software for advanced memory tech.
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
Designs and implements high-performance RISC-V CPU and SoC RTL modules using SystemVerilog, collaborating with architects, verification, and backend teams to optimize performance, power, and area.
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