Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Verify custom silicon designs for Google Cloud, building constrained-random test environments in SystemVerilog/UVM to uncover bugs and ensure tape-out readiness.
Designs and implements FPGA firmware for AMD/Xilinx Zynq UltraScale MPSoC using Vivado, HDLs, and embedded Linux tooling (Yocto/PetaLinux) in a Central London office.
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.
Build and deploy AI agents that automate silicon IP design using RAG, agentic workflows, and EDA tool integration to accelerate spec-to-netlist pipelines.
Design verification engineer building PCIe interconnect IP testbenches using UVM/SystemVerilog to validate high-performance ASIC features for AMD’s GPUs, APUs, servers, and consoles.
Verify next-gen PCIe controller designs for AMD’s SoCs, using SystemVerilog/UVM testbenches and low-power techniques to ensure performance and power targets for AI, gaming, and server chips.
Design verification engineer at AMD, building and automating tests for next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
Design and verify next-gen ASICs using SystemVerilog and UVM, collaborating with architects and engineers to ensure first-pass silicon success.
Design Verification Engineer at AMD builds and runs testbenches in SystemVerilog/UVM to validate DDR5/LPDDR5 memory interfaces and DFI protocols for server products.
Lead verification of DDR5/LPDDR5 memory interfaces for server products using SystemVerilog, UVM, and formal methods; mentor engineers and collaborate with hardware, firmware, and software teams.
Design Verification Engineer at AMD building and running testbenches for DDR5/LPDDR5 memory interfaces using SystemVerilog, UVM, and C/C++ to validate server memory products.
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
SMTS Logic Design Location: Montreal, UNAVAILABLE, CA Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of…
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Design verification engineer building and running SystemVerilog/UVM testbenches to validate DDR5, LPDDR5/6, and DFI memory interfaces for AMD’s server products.
Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.
Leads verification strategy for complex IC designs, guiding teams to build test environments, debug RTL, and improve coverage using UVM, SystemVerilog, and RISC-V protocols.
Design and verify high-bandwidth memory (HBM) digital logic using Verilog/SystemVerilog, collaborating with verification and physical-design teams to ensure robust closure and post-silicon debug.
We couldn't check your fit for this role — add a CV to your profile to see it next time.