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Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads the design and implementation of high-performance digital IPs and SoC subsystems for AI infrastructure connectivity chips using Verilog/SystemVerilog, CXL, PCIe, and Ethernet.
Principal Digital Design Engineer at Astera Labs in Taipei will architect and implement complex digital blocks for high-performance AI connectivity silicon, owning designs from micro-architecture through silicon bring-up. Core technologies: RTL design, Cadence/Synopsys flows, PCIe/Ethernet/DDR protocols, timing closure, DFT, and UVM verification.
Senior digital design engineer at Astera Labs owning complex digital blocks for AI connectivity silicon — from micro-architecture and RTL implementation through timing closure, DFT, verification support, and silicon bring-up — targeting PCIe Gen 6/7, CXL, UALink, Ethernet, and DDR protocols on sub-7nm nodes using Cadence/Synopsys flows.
Architects and implements complex digital blocks for Astera Labs' AI connectivity silicon, owning designs from micro-architecture and RTL through timing closure, DFT, verification, and post-silicon bring-up for protocols like PCIe Gen 6/7, CXL, UALink, UCIe, Ethernet, and DDR, using Cadence/Synopsys flows on advanced CMOS nodes.
Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable…
AMD's Cores team in Fort Collins, CO seeks a senior RTL design engineer to design high-performance, energy-efficient cache and routing-fabric microarchitecture for next-generation CPU cores, collaborating with architecture, physical design, verification, and DFT teams. Key tech: digital RTL design, Verilog, and cache/coherency architecture.
Renesas is a global semiconductor company providing hardware and software solutions for various cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications.…
Quantum Source is hiring a Senior FPGA Team Leader in Rehovot, Israel to lead FPGA and electronics development for a photon-atom quantum computer. The role is hands-on: owning FPGA architecture and RTL, PCB lifecycle from schematic to bring-up, and system integration using Verilog/VHDL, FPGAs, and board-level electronics.
The Memory Technology Group is at the core of Sandisk's engineering organization. We are building a cutting edge 3D memory in our multi-billion dollars lab. Our memory provides performance, power, and endurance at…
Technical lead for RTL design of networking ASICs in Google's Server Chip Design team: defining block-level architecture, coding and debugging RTL (Verilog/SystemVerilog/VHDL), running simulations and Lint/CDC/FV checks, and participating in synthesis, timing/power, and silicon bring-up from spec to production.
Manages and mentors a team of RTL design engineers developing compute-core IP for Google's Tensor Processing Units (TPUs), owning micro-architecture specs, design reviews, and cross-functional planning for power, performance, and timing. Requires deep ASIC/SystemVerilog chip design experience plus people-management background.
A silicon SOC integration engineer who stitches subsystems into the full-chip top-level RTL for MatX's AI training chips, building automation for on-the-fly SOC RTL generation and aligning clock/reset, timing, and floorplan connectivity with physical design. Core tools: SystemVerilog, Python/Perl, and SOC integration/verification flows.
You will define architectures and implement RTL for AI acceleration IPs and core SoC components. You will coordinate with verification, SoC integration, software, and DSP engineers, optimize hardware implementations of…
You will define SoC or subsystem architecture, create RTL designs, and integrate high-performance AI accelerator systems. You will coordinate IP integration with verification, software, and backend functions, work with…
You will design SoC top-level architecture and integrate RTL. You will integrate CPU, AI, and memory subsystems; define bus interconnects; manage clock, reset, and power domains; perform synthesis, timing, and power…
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