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Lead end-to-end execution of complex SoC and processor programs, owning architecture through commercialization while aligning cross-functional teams and managing technical/business risks.
Designs and optimizes advanced ASICs for Cisco’s networking hardware, using EDA tools like Innovus and Tempus to perform RTL-to-GDSII flows, timing closure, and power integrity analysis.
Design and implement high-performance CPU frontend features for RISC-V cores using Chisel/Verilog, focusing on instruction fetch, decode, and branch prediction while collaborating with verification and physical design teams.
Lead a team designing CPLD/FPGA logic for server and storage products using Verilog/VHDL, I2C, SPI, and validation flows.
Design and implement timing-critical RTL blocks for memory/storage chips using SystemVerilog, focusing on latency, CDC, reset logic, and PVT-aware coding for advanced process nodes.
Designs and validates security IP blocks (e.g., cryptographic accelerators, root-of-trust) for Microsoft’s cloud hardware, collaborating with SoC and firmware teams to deliver secure, high-performance RTL solutions.
Develop and optimize computer vision and video processing algorithms for Qualcomm’s Snapdragon-powered devices, mapping them to hardware accelerators and deploying on-device.
Build AI-driven tools to automate RTL front-end design flows using agentic frameworks like LangChain/CrewAI, reducing manual effort in synthesis, STA, and verification.
Designs next-gen WLAN hardware at the RTL/IP level, focusing on logic synthesis, timing constraints, and low-power optimization for 6nm+ processes using tools like Genus, Primetime, and Tcl scripting.
Implementation Timing / STA Design Engineer Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area: Engineering…
Design and deploy power-efficient Network-on-Chip (NoC) interconnects for Qualcomm SoCs, focusing on power-performance optimization and low-power techniques across mobile, automotive, and IoT devices.
Video Codec Design Engineer, up to Staff Location: Taipei, Taipei City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group…
Designs and validates RTL for DDR memory interfaces and low-power SoCs, ensuring timing closure and compliance with AHB/AXI protocols.
Lead a team designing custom silicon and SoCs for Google’s AI and cloud infrastructure, overseeing RTL coding, simulations, and physical design to deliver high-performance hardware.
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on microarchitecture, RTL coding, and integration with AI/ML systems.
Designs and implements RTL logic for Intel’s IP blocks, focusing on secure memory access, error handling, and debug/telemetry features to ensure high-performance SoC reliability.
Develops a new automation tool for silicon CAD (chassis automation) to generate RTL, register definitions, and verification collateral from user requirements, collaborating with RTL, verification, and SoC teams using Python, structured schemas, and CI/CD pipelines.
About ChipAgents ChipAgents is reinventing semiconductor design and verification through agentic AI workflows. Founded by leading experts in AI and chip design, we work with top-20 semiconductor companies, major cloud…
Design and verify RTL hardware designs and SystemVerilog/UVM testbenches to train AI agents that automate chip design workflows.
Build and deploy full-stack AI systems that automate chip design workflows using generative models and agentic AI, working directly with customers to integrate solutions.
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