Tech jobs — page 26 · freehire

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Senior DFT (Design for test) Engineer

Open 41d EuropeSenior

Capgemini is hiring a Senior DFT (Design-for-Test) Engineer in Belgrade to perform DFT insertion on advanced-node SOCs — scan compression, JTAG, ATPG, MBIST/LBIST — debug test coverage and timing, and support silicon bring-up, using EDA tools such as Synopsys DFT Compiler, Tetramax, VCS, Tessent and Modus, with Perl/Tcl/Python scripting.

JTAG Perl Python Tcl

VLSI - DFT Architect

Capgemini is hiring a VLSI DFT Architect in Bangalore to lead design-for-test execution across ASIC/SoC programs from architecture to silicon production — defining scan, compression, ATPG, MBIST and JTAG/1500/1687 solutions with EDA tools like TestMAX, Tessent, and Modus, plus TCL/Perl/Python automation, and supporting tape-outs through silicon bring-up.

AI Automation Bash HPC JTAG +4 skills

Senior Network Engineer (1-year contract)

Open 41d APACContractSenior

Capgemini is hiring a Senior Network Engineer on a 1-year contract in Singapore to design, implement, and support secure, mission-critical network infrastructure for Air Traffic Management (ATM) systems, initially on the LORADS-III program. Core tech includes Cisco networking, Linux/RHEL, network security, and scripting (Shell, Perl, TCL/TK).

Agile AI Automation Bash Ccna +11 skills

PD Partition Lead (Physical Design, Semiconductors)

Open 41d HybridEuropeLead

A physical design (PD) lead role at Capgemini Engineering in Katowice, Poland, owning full-chip or block-level physical design in advanced semiconductor nodes (10nm and below) — floorplanning, partitioning, CTS, place-and-route, timing and sign-off closure — with the option to lead other PD engineers.

AI Generative AI Performance Management Perl Python +2 skills

CELESTICA ELECTRONICS (S) PTE LTD

Test Engineer

Test Engineer at Celestica in Singapore supporting test and software-load engineering for high-quality server and storage products. Day to day involves maintaining network/test server infrastructure, running automated OS and software load processes (Windows, Linux), and developing test automation in TCL, Python, or Go per customer specifications.

Automation Cloud Linux Networking Python +2 skills

Altera Corporation

Full Chip Timing Modeling and Integration Engineer

Develops timing methodologies and performs hands-on full-chip static timing analysis for Altera's next-generation FPGAs on advanced process nodes — building, integrating, and validating high-level timing models with cross-functional, multi-site design teams. Core stack: STA, Liberty/Verilog/SDC, SPICE correlation, Python/Tcl, LVF/POCV.

AI Automation FPGA Machine Learning PCIe +3 skills

133K – 193K $

Ingénieur prototypage et validation FPGA expérimenté H/F

Bull c’est une histoire. Un siècle d’innovation Européenne et un environnement de travail où des experts conçoivent des solutions numériques puissantes, durables et souveraines, permettant aux États et aux industries…

Bash Data Science Ethernet FPGA HPC +4 skills

jobs.hii-tsd.com

Embedded Systems Engineer

Open 11d North AmericaFull-time

Requisition Number: 29345 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Anticipated Salary Range: $72,497.00 - $246,509.00 Security Clearance: Ability to Obtain Level of Experience: Mid This…

AI Assembly Bash Big Data C++ +11 skills

jobs.hii-tsd.com

Digital Design Engineer

Open 9d North AmericaFull-time

Requisition Number: 29344 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Anticipated Salary Range: $72,497.00 - $246,509.00 Security Clearance: Ability to Obtain Level of Experience: Mid This…

AI Assembly Bash Big Data C++ +11 skills

jobs.advanced-energy.com

Sr Firmware Engineer, FPGA

ABOUT ADVANCED ENERGY Advanced Energy (Nasdaq: AEIS) is a global leader in the design and manufacturing of highly engineered, precision power conversion, measurement and control solutions for mission-critical…

Agile Bitbucket Confluence C++ FPGA +9 skills

Arista Networks

FPGA Design Engineer

Open 15d HybridNorth America Licensed UK sponsor Canada LMIA employer Ireland permit employer

Designs and verifies control-path FPGA RTL (Verilog/SystemVerilog) for Arista's data center Ethernet switch platforms, owning the full lifecycle from architecture and board review through synthesis, timing closure, verification, and lab bring-up in collaboration with hardware, software, and manufacturing teams.

AI Arista Automation Bash Ethernet +11 skills

Arista Networks

FPGA Design Engineer

Open 15d HybridNorth America Licensed UK sponsor Canada LMIA employer Ireland permit employer

Design and verify high-performance control-path FPGAs for Arista's data center Ethernet switch platforms, owning the full lifecycle from Verilog/SystemVerilog RTL development and verification through synthesis, timing closure, and system bring-up. On-site role in Santa Clara, CA requiring 5+ years of RTL design experience.

AI Arista Automation Bash Ethernet +11 skills

110K – 170K $

Advanced Micro Devices, Inc

Senior ASIC RTL Design Engineer, AI Networking IP

Open 15d North AmericaSenior

Senior ASIC RTL design engineer on AMD's IP team building high-performance networking and communications IP cores for AMD chips. Day to day: write synthesizable Verilog/SystemVerilog RTL, leverage AI coding tools for productivity, support synthesis/timing closure, verification regressions, and emulation, and mentor junior designers.

AI Asic Atlassian Bash ChatGPT +14 skills

Advanced Micro Devices, Inc

Memory PHY Principal Design Engineer

Open 15d North AmericaPrincipal

Seasoned engineer to architect and develop high-speed memory interface IP (LPDDR/DDR) at AMD — defining digital PHY architecture and microarchitecture, leading RTL implementation and firmware integration, and guiding synthesis, timing closure, and power optimization through silicon. Core tech: Verilog/SystemVerilog, UPF, Python/Perl/Tcl.

AI Firmware Perl Python Rtl +4 skills

Advanced Micro Devices, Inc

Embedded Systems Engineer

Open 15d North America

Senior IC at AMD owning embedded designs for post-silicon system-level validation and board bring-up on FPGA/SoC platforms: writing bare-metal and Yocto-based embedded Linux firmware for ARM/RISC-V cores, debugging failures spanning silicon, firmware, and OS, and driving validation signoff across networking, storage, automotive, aerospace, and AI/ML workloads. On-site in San Jose; no visa sponsors

AI Automation Bash C++ Embedded Linux +13 skills

SambaNova Systems

Design Verification Engineer

Open 67d North AmericaFull-time Licensed UK sponsor H-1B sponsor history

Design Verification Engineer builds SystemVerilog/UVM test environments to verify AI chip control, initialization, and state transitions for SambaNova’s RDU chip.

Agentic AI AI Bash Firmware GPU +6 skills

120K – 200K $

Western Digital

Quantum Device Design Engineering Scientist

Open 15d RemoteNorth America Licensed UK sponsor

Western Digital is hiring a research scientist to design superconducting quantum computing devices — qubits, microwave resonators, readout/coupling architectures, and QPU packaging. Day to day involves conceiving, simulating (EM), and refining device layouts, working with materials/measurement scientists, and programming in languages like Python, Rust, TCL, or C.

Assembly FPGA Microcontrollers Python Rust +1 skills

FPGA Designer

Open 64d North America

Building the space between proven and possible, MDA Space is a trusted mission partner to the global space industry. A robotics, satellite systems and geointelligence pioneer with a 55-year+ story of world firsts and…

Accessibility Asic Confluence Embedded Software FPGA +8 skills

Ingénieur de Production DevOps H/F

Open 15d Europe

DevOps production engineer at TUANIS Conseil, a 100-person French IT services firm, hired for a mission with a banking-sector client in Lyon. Day to day: keep critical production applications and infrastructure running, automate deployments and batch jobs, and improve CI/CD. Core stack: Linux, Control-M, Jenkins, shell scripting, Git.

Ansible Bash CI/CD Control-M DevOps +13 skills

Silicon Intern - Physical Design & DFT (USA)

Open 17d North AmericaInternshipIntern

This internship focuses on transforming RTL into manufacturable silicon through physical design (synthesis, PnR, timing closure) and Design For Test (DFT) methodologies. Interns work with industry-standard EDA tools like Synopsys or Cadence and script in Python, Tcl, or Perl to optimize AI hardware performance and testability across multiple US-based design centers.

AI Bash JTAG Machine Learning Networking +3 skills

50 – 70 $ / hr