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Om Advenica På Advenica gör vi cybersäkerhet på riktigt. Vi levererar cybersäkerhetslösningar inom kryptering och nätverkssegmentering med den högsta nivån av godkännande från EU och Sverige. Med decenniers erfarenhet…
Leads verification of high-speed I/O (HSIO) PHY interfaces for Google's custom silicon, owning sub-system and SoC-level testbench bring-up, running RTL/gate-level/timing regressions, and debugging complex waveforms through silicon bring-up. Core stack: SystemVerilog, C, OVM/UVM, and protocols like USB, PCIe, UFS, and MIPI.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
You Are: You are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/SystemVerilog and are experienced in developing and managing…
Hello, This is Jayesh from IntelliPro group. I found your profile in a job portal and wanted to discuss about the below role which can be a good fit for your career. Kindly go through below job description and let me…
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Design verification engineer Qualcomm is a company of inventors that unlocked 5G, ushering in an era…
Senior engineer at Airbus Defence and Space in Ulm designing, building, and maintaining sovereign GenAI services, chatbots, and autonomous agents for internal software development, including on-prem LLM infrastructure (Docker/Kubernetes), RAG pipelines, and MCP tooling under strict security standards.
Senior engineer at Airbus Defence and Space in Ulm who designs, builds, and deploys GenAI services, chatbots, and autonomous AI agents (including RAG pipelines and MCP tools) for internal software development in a secure on-premise environment. Core stack: Python, LLM inference frameworks (vLLM/SGLang), vector DBs, Docker/Kubernetes.
Designs, verifies, and tests FPGA-based RTL for satellite systems, collaborating with hardware, software, and DSP teams to meet performance and radiation-mitigation requirements.
Senior FPGA Engineer who architects, designs, verifies, and tests RTL for FPGAs in spacecraft and ground stations, including software-defined radios, avionics, and radiation mitigation schemes. Day-to-day work spans Verilog/SystemVerilog, C/C++ bit-accurate modeling, and Xilinx toolchains in close collaboration with DSP and embedded software teams.
A 12-week, salaried associate role for new grads at satellite maker Astranis in San Francisco: you'll write RTL for FPGAs, work across multiple toolchains, interface FPGAs with high-speed data converters and memories, and write test software alongside electrical and software engineers. Requires Verilog/SystemVerilog proficiency and U.S. person status.
A 12-week salaried associate role at satellite maker Astranis in San Francisco for new grads: designing RTL for FPGA-targeted applications, interfacing FPGAs with high-speed data converters and memories, and writing software to test RTL in hardware alongside electrical and software engineers. Core tools are Verilog/SystemVerilog and FPGA toolchains like Xilinx Vivado.
A 12-week summer internship in San Francisco working on FPGA development for Astranis satellites: writing RTL, interfacing FPGAs with high-speed peripherals like data converters and memories, and testing RTL in hardware alongside electrical and software engineers.
A 12-week, hourly internship on Astranis's FPGA team in San Francisco: the intern writes RTL for satellite-targeted FPGAs, interfaces them with high-speed data converters, memories and MCUs, and builds test software alongside electrical and software engineers. Open to current students with US citizenship or a green card.
Entry-level Study Engineer/Data Scientist at Airbus Defence and Space in Immenstaad am Bodensee (Friedrichshafen), running theory- and data-driven simulation studies of complex 'systems of systems' for Bundeswehr, NATO and EU defense projects. Core work: AI/ML and agent-based algorithms, modeling, and big-data analysis using C++ and Python in an in-house simulation framework.
A study engineer/data scientist at Airbus Defence and Space in Immenstaad designs and runs theory- and data-driven simulation studies for military operational analysis (Bundeswehr, NATO, EU projects), developing AI/ML algorithms and mathematically modeling complex 'systems of systems' in an in-house C++/Python simulation framework, plus big-data analytics and client presentations.
Das Leibniz-Institut für Bildungsverläufe sucht zum 01.12.2026 für die Dauer von zunächst 12 Monaten eine Studentische Hilfskraft (w/m/d) im Projekt AI-SIC Das Leibniz-Institut für Bildungsverläufe (LIfBi) mit rund 250…
Summer 2027 hardware engineering internship at Hudson River Trading, where interns design and verify FPGA/ASIC compute engines for low-latency algorithmic trading — writing SystemVerilog design code and Python-based modeling/verification environments on critical, real-time trading infrastructure.
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling…
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