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Senior Principal Firmware Engineering Lead Location: US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDG Time Type: Full time Job Description Date Posted: 2026-07-23 Country: United States of America Location:…
Hardware Engineer Location: Chicago, United States Department: Development (Group) IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next generation of custom ASICs that power our…
Digital Design Engineer Location: Santa Clara, CA Department: External - Client Requirement Job description : Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for…
FPGA Verification Engineer Level 3/4 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR…
FPGA Verification Engineer Level 5 - Linthicum Location: United States-Maryland-Linthicum Time Type: Full time Job Description RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START:…
Senior Engineer - ASIC Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow With Us: About this opportunity: We are starting a new Silicon R&D center in…
Experienced Engineer - FPGA Verification Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Join our Team About this opportunity: Are you passionate about driving innovation…
Analog Front End Architect (Tektronix) Location: Beaverton, OR, United States Department: Engineering Work Location: hybrid Job Title: Analog Front End Architect Location: In Person or Hybrid (Beaverton, OR)…
Designs and optimizes high-performance coherent interconnect IP and last-level cache blocks for Samsung's advanced semiconductor products, collaborating with architects, verification, and implementation teams.
Leads the launch of Cisco networking hardware and software products, coordinating engineering, supply chain, and manufacturing teams to meet cost, quality, and time-to-market goals.
Designs and optimizes high-speed digital logic for AMD’s mixed-signal IO interfaces, using Verilog RTL and ASIC flows to deliver silicon-ready solutions.
Lead verification of custom silicon powering Meta's data center infrastructure, designing UVM-based environments and ensuring first-pass silicon success for AI/ML, networking, and storage ASICs.
itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable,…
Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental…
About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand…
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Designs and optimizes digital circuits for ASICs/ICs, ensuring low power, performance, and compliance while collaborating with analog and test teams.
Senior Software Engineer at NVIDIA designing and developing tools for RTL generation and automated workflows in C++, with a focus on ASIC design and Verilog RTL for GPU and AI hardware.
Senior AI engineer building LLM-powered agents and RAG systems to automate SOC design workflows like design review, CI/CD gating, and cross-team reporting using Python, LangChain, and vector databases.
Senior engineer designing and integrating high-performance System-on-Chip (SOC) components for NVIDIA’s next-gen GPUs, using RTL design, automation, and scripting to streamline chip development.
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