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Designs and verifies FPGA-based control logic for aerospace engine controllers and avionics, using VHDL/Verilog and tools like Xilinx Vivado.
Design engineer role building next-gen storage and memory controller SoCs, owning IO/pad-ring planning and physical-design hand-off for high-performance data-center products.
Design and implement Digital Thread solutions connecting Siemens Teamcenter, ERP, MES, and other enterprise systems to improve data continuity and automation across engineering and manufacturing workflows.
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
. We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip…
Mixed Signal Logic Design Engineer Location: India, Bangalore Time Type: Full time Job Description Job Details: Job Description: The Role and Impact As a Mixed Signal Logic Design Engineer, you will play a pivotal role…
Lead the design of next-gen ASIC IP for AI-driven data movement, collaborating across teams to deliver high-performance, secure, and power-efficient silicon solutions for AMD’s server, data center, and embedded products.
Design and run verification environments for ASIC/FPGA chips using SystemVerilog/UVM, then execute test cases to ensure hardware correctness.
Role Overview We are looking for a highly skilled Senior Staff Physical Design Engineer to drive end-to-end physical implementation for advanced semiconductor designs across cutting-edge technology nodes. The ideal…
Lead a team to design and deliver embedded memory compilers (SRAM, ROM, register files, DPRAM) for SoC integration, setting PPA targets, customer requirements, and silicon validation.
Principal engineer designing and optimizing physical layouts for Microsoft's next-gen AI chips, ensuring high-performance, low-power, and manufacturable designs using industry-standard EDA tools.
Develop and customize PLM software integrations for clients in automotive, aerospace, energy, and machinery, focusing on engineering design and manufacturing workflows.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Designs and verifies advanced semiconductor mask layouts for high-performance processors, collaborating with circuit teams to ensure tape-out readiness using industry-standard tools.
Design and optimize clocking and physical design flows for complex SoC/ASIC chips using industry-standard EDA tools and scripting.
Designs and implements physical layouts for high-performance chip IP, owning floorplanning through GDS tape-out on advanced nodes (28nm or below).
Principal Engineer designs and verifies memory controller IP for DDR/HBM/GDDR DRAM, building SystemVerilog testbenches and coverage-driven regression suites.
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
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