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Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.
Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities:…
Build and maintain UVM/SystemVerilog testbenches to verify PCIe and memory-subsystem RTL, collaborating with architects and post-silicon teams to ensure robust, high-performance designs.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Senior Engineer - Low Power Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow with us About this Opportunity Join Ericsson's cutting-edge journey to shape the…
Senior Engineer - Physical Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow with us About this Opportunity Join Ericsson's cutting-edge journey to shape the…
Designs and implements high-performance memory compilers and RTL blocks for custom SoCs, collaborating with architecture, verification, and physical design teams to deliver silicon-ready IP.
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
Designs and validates chip-level test structures (JTAG, MBIST, scan/ATPG) to ensure silicon quality and manufacturability, collaborating with design and verification teams.
Lead end-to-end ASIC physical design from RTL to GDSII tapeout, optimizing power, performance, and area using Cadence/Synopsys flows for high-security microelectronics.
Designs and verifies next-gen high-speed switch silicon chips for NVIDIA’s networking unit, focusing on throughput, latency, and power efficiency.
Designs and validates high-speed optical communication chips, writing RTL, running simulations, and debugging silicon to meet power and performance targets.
Lead digital RTL design for power-management ICs, defining architectures for embedded cores, control loops, and interfaces while collaborating with analog and verification teams.
Designs and implements high-bandwidth memory SoC physical layouts, using EDA tools to optimize performance, power, and area while integrating complex IP and ensuring manufacturability.
Designs and implements ASIC/SoC RTL (Verilog/SystemVerilog) for high-performance SSD controllers, collaborating with verification, validation, and firmware teams to deliver next-gen enterprise and AI data center storage solutions.
Designs and verifies custom silicon for Google's TPU AI accelerators, focusing on SoC-level RTL, architecture, and integration within AI/ML systems.
Principal Engineer leading post-silicon validation and testing of next-gen coherent DSP ASICs for AI and optical networking, ensuring first-silicon readiness and production deployment.
Design verification engineer at AMD, building and running tests to validate next-generation x86 CPU cores using C++, Verilog, and SystemVerilog.
Builds AI-powered tools that automate and accelerate semiconductor chip design and verification workflows using agentic AI and full-stack software engineering.
RTL Design Engineer Location: Bengaluru, Karnataka, India Workplace: on_site Employment Type: full
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