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On-site co-op/internship in Ottawa embedded with Q-Block's firmware and hardware engineers, writing C/C++ firmware for microcontrollers, contributing to FPGA/digital logic, and supporting PCB bring-up and testing on the company's quantum hardware platforms.
Software Developer at Johns Hopkins APL building C/C++ desktop and embedded applications and digital signal processing (DSP) algorithms for next-generation electronic warfare (EW) systems, validating work in lab demos and field tests. Requires U.S. citizenship and eligibility for a Secret clearance; pays $100k-$245k.
Remote junior hardware/digital design engineers help build a 200,000-image dataset of circuit, timing, and state diagrams, pairing each image with Verilog/SystemVerilog HDL code or an accurate English technical description. Indicative pay is about USD 20/hour, with 50-100 experts to be onboarded.
Fully remote contractor role creating a dataset of digital-design diagrams (circuit, timing/waveform, and FSM state diagrams) paired with either Verilog/SystemVerilog code or English technical explanations, for a DATAmundi.ai dataset project under Summa Linguae Technologies. Pays about $20/hour; seeks people with digital logic, FPGA/ASIC, and HDL fundamentals.
Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Ingénieurs de…
The Software and Electronics Engineering Group collaborates with every research area at the Laboratory to create systems that accomplish their objectives in real-world scenarios and in unpredictable surroundings. Our…
Über den Bereich Das Team "HW-Development" ist für die Entwicklung gesamter Geräte inklusive Mechanik Design, Circuit Board Assemblies (CBAs), Programmable logic devices (PLDs) z.B. FPGA und Erstellung von…
In Capgemini Engineering , leader mondiale nei servizi di ingegneria, uniamo un team globale di talenti dell’ingegneria, scienza e architettura per aiutare le aziende più innovative del mondo a liberare il loro…
Six-month internship on Arm's Solutions Engineering team in Budapest: take part in the SoC design process using Arm IP, write RTL in SystemVerilog, run EDA tools, and debug designs, using AI-assisted tooling. Pays HUF 5,250,000 per annum, with a possible path to a Graduate role.
An ~6-month internship (full- or part-time, hybrid) at ARM's Budapest office where the intern develops testbenches and test cases to verify hardware designs and trials new verification processes and flows. Core tech includes VHDL/Verilog simulation, C/C++, and UNIX/shell, with exposure to EDA tools and AI-assisted development.
Applications Engineer at Arm in Budapest supporting global customers on Arm CPU & System IP: investigating issues with RTL simulations, mentoring partners on IP integration and performance, delivering onsite/remote technical training, reviewing customer SoC builds, and building knowledge-base articles and internal tooling.
Job DescriptionJob Description Job Title: Senior FPGA Engineer Department: Engineering Reports To: Functional Team Lead / Program Manager FLSA Status: Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are…
Job ID: Posted: Posted 4 Days AgoStart Date: Location: US-TX-MCKINNEY-513WH ~ 2501 W University Dr ~ WING H BLDGCountry: United States of AmericaTime Type: Full timeDate Posted: Country:United States of America…
About Optivolt Optivolt’s mission is to overshoot humanity’s energy supply by reimagining solar. America is at an inflection point. We need reliable energy fast. The grid is aging. And solar, the only technology that…
About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans…
Intégrez la Direction qui, tout au long du cycle de développement, conçoit, fabrique et teste des installations de tir et des calculateurs avioniques. Au sein du département “Installations de tir et Avioniques”, vous…
Customer-facing applications engineer at AMD supporting Adaptive SoC and AI Edge devices: owns escalated customer cases from bring-up through production, with a focus on silicon debug (root-causing failures across processing subsystems, interconnect, memory and boot path) plus owning the embedded Linux release and customer documentation. Core stack: Vivado/Vitis, Yocto/PetaLinux, SystemVerilog/Ver
Why Castelion, Why Now Castelion is moving incredibly fast to develop and deliver advanced defense systems at a time when execution matters more than ever. We believe focus, ownership, and excellence are decisive…
Designs and optimizes FPGA-based hardware for ultra-low-latency trading systems, coding in VHDL and collaborating with software teams to enhance market-making infrastructure.
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