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Design and integrate custom TPU silicon for AI/ML workloads, owning multi-chiplet SoC architecture, interposer planning, and RTL integration to deliver high-performance hardware at scale.
Lead a team designing secure silicon IP blocks for chips, using Verilog/VHDL, cryptography, and formal verification in a hybrid office setting.
FPGA Prototyping Staff Applications Engineer Location: Bengaluru, India We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We…
FPGA Prototyping/ Emulation Staff Application Engineer Location: Bengaluru, India We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive…
Front-End & Back-End SoC Engineering, Principal Engineer Location: Munich, Germany We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
SOC Engineering, Staff Engineer - RTL Design Location: Noida, India Job Title: RTL Design Engineer, Staff Level - SoC Design We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling…
SOC Engineering, Sr Staff Engineer- RTL Design Location: Noida, India Job Title: SoC RTL Design Engineer, Sr Staff We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to…
Leads a team to design and optimize CPU microarchitecture, translating specifications into high-performance, low-power RTL designs using industry tools and delivering GDS for manufacturing.
Lead a global team to deliver advanced-node High-Performance Computing (HPC) and AI SoCs from RTL through GDSII and tape-out, optimizing Power, Performance, and Area (PPA) while scaling backend engineering processes.
Designs and verifies high-speed protocol IP (e.g., PCIe, Ethernet) for emulation and prototyping tools using Verilog, UVM, and FPGA flows.
Designs and implements advanced IP components for next-generation System-on-Chip (SoC) architectures using Verilog HDL, low-power techniques, and ARM-based design flows.
Lead architecture and RTL design for Automotive Ethernet PHY subsystems, implementing PCS pipelines, safety mechanisms, and ISO 26262-compliant logic in Verilog/SystemVerilog.
ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This approach has led us to a seventy-five-year history of delivering outstanding solutions to customers in virtually every…
- Bachelor's degree or above in computer science, electrical engineering, or related field - - 3+ years of hands-on post-silicon validation or system validation engineering experience - - Strong programming skills…
- 5+ years of technical product or program management experience - 7+ years of working directly with engineering teams experience - 3+ years of software development experience - 5+ years of technical program management…
- Bachelor's degree in Electrical Engineering or a related field - Knowledge of UVM and Matlab - Experience developing products for volume production - Experience low power design techniques - Master's degree…
Designs and validates next-generation wireless radios for Apple’s SoCs, focusing on RF/analog/mixed-signal circuits and system-level modeling in advanced CMOS nodes.
FAST Lab – Senior FPGA Engineer Location: Merrimack, New Hampshire, United States Category: Engineering & Technology Employment Type: Full-Time Job Description Be a part of something bigger. At BAE Systems’ FAST…
FAST Lab – Entry Level FPGA Engineer Location: Merrimack, New Hampshire, United States Category: Engineering & Technology Employment Type: Full-Time Job Description Be a part of something bigger. At BAE Systems’…
Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.
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