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Contract FPGA engineers to design and implement Verilog/VHDL for satellite telecoms projects using Xilinx ISE and SystemVerilog.
Application Engineer – AI & Verification Solutions Location: PETAH TIKVA Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Application Engineer I: Systems Verification - Emulation Location: BELO HORIZONTE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Design and implement firmware for high-speed SERDES PHY IP, collaborating on architecture, verification, post-silicon validation, and customer deployment using C/C++ and Python.
Lead verification of low-power SoC features using UPF/CPF, building SystemVerilog/UVM testbenches and power-aware test plans to ensure robust, energy-efficient silicon.
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Design and verify complex silicon subsystems for Arm-based platforms using SystemVerilog/UVM, ensuring functionality, performance, and coverage closure.
Designs and verifies digital circuits for IoT and automotive chips using VHDL/Verilog, SystemVerilog, and Python, with a focus on signal processing and embedded software integration.
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
Design Verification Engineer builds UVM testbenches and runs pre-silicon verification for FPGA DFT logic like scan, MBIST, and JTAG to ensure silicon quality before tape-out.
Designs and verifies digital IP blocks and SoC architectures using SystemVerilog/UVM to ensure functional correctness of high-speed ASIC components like Ethernet switches and PCIe controllers.
Build Python automation tools, dashboards, and AI-assisted workflows for semiconductor test development, then validate and analyze results to improve efficiency.
Design and verify FPGA-based systems using VHDL/SystemVerilog for aerospace/defense applications, collaborating with hardware and systems teams to meet DoD requirements.
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.
Designs and builds software tooling, firmware, and infrastructure to accelerate semiconductor development cycles, working closely with hardware teams in EDA, verification, or post-silicon environments using C, C++, and Python.
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
We are looking for an FPGA Engineer to join our team and work on high-performance FPGA/SoC solutions, with a strong focus on digital signal processing (DSP), algorithms, and RF applications . Location This is a…
Hardware Engineer Intern contributing to FPGA development and hardware improvements at a global trading firm, using VHDL/Verilog and collaborating with trading and tech teams.
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