Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
The SSD Tester Development Engineer will design and maintain next-generation NVMe SSD testing equipment, focusing on system architecture, PCIe high-speed circuits, microcontroller firmware, and FPGA development.
Silicon Quantum Computing (SQC) is at the forefront of global efforts to build the world’s first commercial-scale quantum computer, while delivering quantum-enhanced AI and simulation products to customers today.…
Job Description Passionate about building SoC verification platforms? Eager to expand into firmware, software and performance analysis? Arm’s System-on-Chip(SoC) Performance Analysis Team in Central Technology group…
This role involves designing and maintaining verification plans and SystemVerilog/UVM testbenches for ARM's scalable coherent mesh network interconnects. Engineers will collaborate with architects to debug functional failures and improve verification methodologies for high-performance compute and AI applications.
Designs and verifies high-performance ASIC/SoC chip systems using Verilog/SystemVerilog, UVM, and RTL methodologies in a collaborative engineering environment.
Designs and verifies digital circuits for motor controllers, using Verilog and FPGA tools, and collaborates on synthesis, timing, and chip implementation.
Designs and implements high-performance digital logic for communication and optical networking chips using Verilog/SystemVerilog, guiding the RTL from specification to tapeout while collaborating with cross-functional teams.
Designs and verifies RTL (Verilog/SystemVerilog) for DSP and photonics ICs, focusing on high-speed datapaths and low-latency logic while collaborating with cross-functional teams.
Designs and verifies digital circuits for power systems using Verilog, RTL, and FPGA tools, while guiding junior engineers and collaborating with backend teams on synthesis and timing analysis.
Designs and verifies low-power digital subsystems and mixed-signal SoCs using SystemVerilog/VHDL, synthesis, and verification tools in a semiconductor company.
Digital Design Engineer responsible for SoC/MCU digital sub-circuit development including RTL coding in Verilog/SystemVerilog, synthesis, STA, formal verification, DFT, and post-silicon validation at NXP's Catania site.
Lead the full digital IC design flow for complex SoC microcontrollers at NXP's Catania site, from architecture through RTL coding (Verilog/SystemVerilog), synthesis, STA, formal verification, and post-silicon debug.
ASIC Design Engineer working on mixed-signal chips for GPU power delivery and management, defining micro-architecture and developing RTL behavioral models through the full ASIC design flow to tape-out.
The Senior Design Engineer will design and verify high-performance RISC-V CPU cores for automotive and IoT SoCs. The role focuses on microarchitecture development, RTL coding, PPA optimization, and comprehensive functional verification.
This internship role involves assisting with the design, simulation, and verification of digital integrated circuits using Verilog or VHDL. Interns will work on FPGA prototyping, digital modeling, and timing analysis alongside experienced engineers.
Embedded Software Engineer developing firmware and middleware for quantum computing hardware in C/C++/Rust and Python, working with ARM microcontrollers and real-time systems.
Senior FPGA Engineer designing, developing, and debugging FPGA implementations for power delivery systems in semiconductor manufacturing, using VHDL, Verilog, MATLAB/Simulink, Python, and C++.
This role involves developing and sustaining FPGA firmware and embedded software for flow cytometry instruments, focusing on high-throughput data acquisition and hardware control. The engineer will work with Verilog/SystemVerilog and embedded systems to ensure reliable instrument performance in a laboratory environment.
The Senior Staff Digital Design Engineer will lead the design, implementation, and verification of DSP algorithms and digital control logic for audio processing within ASIC systems. This role involves the full ASIC design flow, from specification to silicon bring-up, utilizing expertise in digital signal processing and mixed-signal integrated circuits.
Own FPGA firmware and embedded software for flow cytometry instruments, sustaining legacy Verilog/SystemVerilog codebases and building real-time acquisition pipelines on FPGA with embedded Linux/RTOS integration.
We couldn't check your fit for this role — add a CV to your profile to see it next time.