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Job DescriptionJob Description Job Title: Senior FPGA Engineer Department: Engineering Reports To: Functional Team Lead / Program Manager FLSA Status: Exempt / Full-time Salary Range: $120k - $150k Annually ROLE We are…
Job ID: Posted: Posted 4 Days AgoStart Date: Location: US-TX-MCKINNEY-513WH ~ 2501 W University Dr ~ WING H BLDGCountry: United States of AmericaTime Type: Full timeDate Posted: Country:United States of America…
About Optivolt Optivolt’s mission is to overshoot humanity’s energy supply by reimagining solar. America is at an inflection point. We need reliable energy fast. The grid is aging. And solar, the only technology that…
About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans…
Intégrez la Direction qui, tout au long du cycle de développement, conçoit, fabrique et teste des installations de tir et des calculateurs avioniques. Au sein du département “Installations de tir et Avioniques”, vous…
Customer-facing applications engineer at AMD supporting Adaptive SoC and AI Edge devices: owns escalated customer cases from bring-up through production, with a focus on silicon debug (root-causing failures across processing subsystems, interconnect, memory and boot path) plus owning the embedded Linux release and customer documentation. Core stack: Vivado/Vitis, Yocto/PetaLinux, SystemVerilog/Ver
Why Castelion, Why Now Castelion is moving incredibly fast to develop and deliver advanced defense systems at a time when execution matters more than ever. We believe focus, ownership, and excellence are decisive…
Designs and optimizes FPGA-based hardware for ultra-low-latency trading systems, coding in VHDL and collaborating with software teams to enhance market-making infrastructure.
Designs and implements low-latency hardware trading systems using FPGAs and ASICs, collaborating with traders and software engineers to solve complex financial market problems.
Designs and implements high-speed FPGA-based trading systems to accelerate network infrastructure and trading components, working closely with traders and software engineers.
FPGA Engineer Intern designs high-speed hardware for trading systems, optimizing nanosecond response times and parallelized algorithms in a global financial firm.
Designs ultra-low-latency FPGA-based trading systems in VHDL/Verilog, optimizing hardware for nanosecond-scale financial market applications.
FPGA Internship where the intern builds latency-critical hardware systems for trading, working on parallel algorithms, networking interfaces, and FPGA applications using VHDL/Verilog/SystemVerilog.
Designs and develops high-speed, high-density trading hardware (PCBs, custom silicon, antennas) for financial markets, from schematic capture to production, while collaborating with multidisciplinary teams to optimize performance and latency.
CHAOS Inc. is a global technology company delivering next-generation capabilities to the defense and critical industrial sectors. Founded in 2022 by a seasoned leadership team, CHAOS has quickly become the place where…
Architects, develops, and integrates RTL and reusable IP for Fortaegis' FPGA and ASIC-based semiconductor products — writing SystemVerilog/Verilog, running synthesis and timing closure with EDA tools (Vivado, Synopsys, Cadence), and collaborating with verification, architecture, and software teams. On-site in Amsterdam.
Qui sommes-nous ? : Créée en 2016, KICKMAKER est une communauté de talents aux profils pluridisciplinaires et complémentaires, animés par la même passion pour le développement de produits high-tech et les défis…
Au sein de la Direction des Opérations, vous intégrez l’équipe en charge de la conception et la réalisation d’équipements électroniques embarqués rentrant dans la composition de nos produits. Objectif de votre stage :…
Senior FPGA engineer building high-performance digital systems for defence, aerospace, and industrial automation projects, working on-site in Wrocław. Day to day involves RTL design and verification with VHDL/Verilog/SystemVerilog, Xilinx Vivado/Intel Quartus toolchains, SoC FPGA platforms (Zynq/MPSoC), embedded C/C++ and DSP.
Hands-on FPGA firmware engineer at defense contractor L3Harris in Palm Bay, FL, owning RTL design, timing closure, verification, and board bring-up on AMD Xilinx platforms (Zynq UltraScale+, Kintex, Versal) using Vivado, VHDL/Verilog, and lab tools to deliver mission-critical embedded capabilities.
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