Directs SoC design verification strategy, methodology, and distributed teams at Ayar Labs in Bengaluru (on-site), hands-on with SystemVerilog/UVM verification of complex SoCs integrating ARM/RISC-V subsystems, coherent interconnects, memory, and high-speed I/O (PCIe, CXL, Ethernet, UCIe, SerDes) for AI, networking, and data-center applications.
Sign in to see your match