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Leads DSP system architecture for high-speed optical transceivers (800G/1.6T+), optimizing algorithms like equalization and clock/data recovery while collaborating with hardware/photonics teams to design next-gen optical chips.
AMD is hiring an on-site Technical Program Manager in San Jose to lead a post-silicon silicon engineering group, coordinating cross-functional teams (SW, HW, firmware, validation) to deliver complex ASIC programs. Core stack includes FPGA-based ASIC design cycles, Vivado flows, and project tools like Jira and Confluence.
Designs and builds high-speed electronics and RF systems to control and read out quantum photonic hardware, integrating with optical and cryogenic systems.
GPU Design Verification Engineer on AMD's verification team in Markham, Ontario, driving functional and performance closure on digital design blocks of the Graphics Core IP (GFXIP) using UVM, SystemVerilog, Verilog and C/C++, including AI-driven verification automation. Requires a bachelor's or master's in computer/electrical engineering; visa sponsorship is not available.
Leads Normal Computing's physical design team in Silicon Valley, owning the end-to-end backend ASIC flow from synthesis, floorplanning, and place-and-route through STA timing closure, DRC/LVS signoff, and GDSII tapeout, while hiring, planning tapeout schedules, and collaborating with RTL/architecture teams using tools like Innovus, PrimeTime, and Calibre.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
About NETINT Technologies Inc. NETINT Technologies is a pioneer of computational storage and video processing SoC solutions for cloud and edge computing. Its Codensity portfolio enables enterprise, cloud data centers,…
Digital IC Design Engineer at indie Semiconductor in Aliso Viejo, CA, designing, integrating, and verifying digital IP (MCU and security) for System-on-Chip solutions serving the automotive ADAS market. Day-to-day work spans system architecture, RTL (Verilog) implementation, pre-silicon verification, and supporting productization using Arm Cortex-based designs and Cadence front-end tools.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Sr Application Engineer – Digital Implementation & Physical Design Location: Malaysia Job Overview We…
About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…
The Silicon One Productization team pioneers manufacturing and test solutions that accelerate time-to-market and deliver best-in-class supply chain performance. We are seeking a skilled ASIC Engineer to manage volume…
Job Details: Job Description: Devices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic…
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
Who we are Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, we're on…
NVIDIA is hiring a Senior ASIC Design Engineer in Santa Clara to architect, implement, and verify high-performance, power-efficient RTL for its SoCs and GPUs. Day to day this means RTL design and synthesis, logic and timing verification, and testbench development using Verilog/SystemVerilog, Perl/Python, and tools like VCS, Verdi, and GDB.
Front-end ASIC design engineer at Credo Technology Group who architects, implements, and verifies complex logic blocks for high-speed connectivity chips, supporting integration tasks (Lint, CDC, synthesis, ECO) through tape-out. Core technologies: Verilog/SystemVerilog RTL design and verification, UVM, and scripting in Python, Tcl, Perl, and shell.
IC design verification engineer on Snap's Spectacles team, verifying display integrated circuits for AR eyewear by building UVM/assertion-based testbenches, executing coverage-driven verification plans, and automating flows. Core stack: SystemVerilog/UVM, Siemens Questa, Verilog RTL, and TCL/Python/Perl/Shell scripting on Linux, working on-site 4+ days per week.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Design and develop FPGA-based control systems for quantum computers, implementing signal processing and real-time logic using Verilog/VHDL and Vivado.
Main Supervisor: Dr. Edmond Cretu, Department of Electrical & Computer Engineering, UBC Duration: 2 years Who We Are: Sonus Microsystems and the AdaMist (Adaptive Microsystems) research group at UBC, led by Dr.…
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