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1,226 jobs

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1,226 jobs Posted Sort

Principal Engineer, ASIC Design Verification

NewBe an early applicant APACPrincipal

Ayar Labs is hiring a Principal Design Verification Engineer in Bengaluru to lead verification strategy for its next-generation silicon photonic (co-packaged optics) chip. The role involves architecting scalable UVM testbenches, setting verification methodology, debugging complex hardware issues, automating regressions, and mentoring engineers using SystemVerilog/UVM, protocol knowledge (PCIe, AMB

AI Asic Automation Bash C++ +8 skills

Principal Engineer, Design for Test (DFT)

NewBe an early applicant APACPrincipal

Ayar Labs is hiring a Principal DFT Engineer in Bengaluru (on-site, flexible hours) to lead Design-for-Test architecture, implementation, and silicon bring-up for electro-optical SoCs and chiplet-based systems. Core work spans scan/ATPG, MBIST/LBIST, JTAG, silicon debug, and production test flows with Python/Tcl automation.

AI Asic Automation Ethernet Firmware +4 skills

Sr. Engineer, ASIC Design Verification

NewBe an early applicant APACSenior

Senior ASIC Design Verification Engineer at Ayar Labs (Bengaluru, on-site) doing pre-silicon verification of complex SoCs with digital and mixed-signal blocks: building SystemVerilog/UVM testbenches, test plans and coverage closure for SerDes, parallel-link and on-chip interconnect IP within a small startup IC design team.

AI Asic Python Uvm Verilog

SG ASIC RTL/SoC Design Engineer

NewBe an early applicant APAC

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Integrate and validate IP blocks within the larger system, ensuring…

AI Asic FPGA Image Processing Rtl +3 skills

SG Hardware - Digital Intern

NewBe an early applicant APACInternshipIntern

About the Role We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMem’s AI accelerators. You’ll contribute to RTL design, simulations, and…

AI Asic Bash Python Rtl +3 skills

US 2026 Hardware - Digital Intern

NewBe an early applicant North AmericaInternshipIntern

About the Role We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMem’s AI accelerators. You’ll contribute to RTL design, simulations, and…

AI Asic Bash Python Rtl +3 skills

ASIC RTL/SoC Design Engineer

NewBe an early applicant North America

Responsibilities: Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system, ensuring seamless…

AI Asic FPGA Image Processing Rtl +2 skills

DASH Tech Integrated Circuits

SoC Design Engineer

NewBe an early applicant RemoteWorldwide

We are seeking a talented and motivated SoC Design Engineer to join our dynamic team and play a pivotal role in designing, developing, and optimizing for DASH Tech IC’s innovative platforms. You will direct all aspects…

Asic CAD Fine Tuning Process Improvement Program Management +1 skills

Upscale AI, Inc.

Senior ASIC Frontend Engineer - RTL & SystemVerilog

NewBe an early applicant North AmericaSenior

Upscale AI, Inc. is seeking a seasoned ASIC Design engineer to define micro-architecture for next-generation designs and own RTL entry that meets power, performance, and area targets. You will collaborate with…

AI Asic SystemVerilog

Upscale AI, Inc.

IC - Frontend - Senior Staff Engineer

NewBe an early applicant North AmericaStaff

Why join Upscale AI Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems…

Accessibility AI Asic Networking Perl +2 skills

Advanced Micro Devices, Inc

Staff Design Verification Engineer

Open 24d UKStaff

Design verification engineer at AMD, building and automating testbenches to verify next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.

AI Analytics Asic Automation Bash +13 skills

Leitender Ingenieur für analoges ASIC-Design (m/w/d) (w/m/div.)

NewBe an early applicant HybridEurope

Sind Sie bereit, die Zukunft des Energiemanagements im Automobilbereich neu zu gestalten? Dies ist Ihre Chance, die Entwicklung hochmoderner analoger ASIC-Lösungen maßgeblich voranzutreiben und Innovationen zu…

Asic Cadence Virtuoso Verilog

Lead Engineer Analog ASIC Design (f/m/div.)

NewBe an early applicant HybridEuropePart-timeLead

Are you ready to redefine the future of automotive power management? This is your opportunity to spearhead the development of cutting-edge analog ASIC solutions, driving innovation that powers the next generation of…

Asic Cadence Virtuoso Verilog

Mixed-Signal ASIC Design Engineer for Analog Frontends and ADCs (f/m/div.)

NewBe an early applicant HybridEuropePart-time

Semiconductors are far more than tomorrow’s key technology. They are our core business – already today. Get on board and join us on this journey. Become part of an inspiring team at Bosch committed to develop…

Asic MATLAB Simulink Verilog

REALTEK SINGAPORE PRIVATE LIMITED

Semi-Conductor Senior Design Verification Engineer

NewBe an early applicant APACSenior

JOB DESCRIPTION In this position, the individual thoroughly understands digital design specs of various IP blocks and SoC architecture definition • Develop detailed module level and SoC level testplans for all the…

Asic Ethernet PCIe SystemVerilog Uvm

ASIC Digital Design, Sr Staff Engineer-18490

NewBe an early applicant Staff

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

AI Asic Automation C Embedded Software +4 skills

FPGA/ASIC Design Engineer (Silicon Engineering)

Open 83d North AmericaFull-time

Designs and optimizes FPGAs and ASICs for SpaceX's Starlink network, using Verilog/SystemVerilog and collaborating with cross-functional teams to enhance satellite and ground infrastructure performance.

Asic Bash C++ Firmware FPGA +7 skills

125K – 195K $

Manager, ASIC Design Engineering (Starshield Silicon)

Open 83d North AmericaFull-time

Lead a team designing ASICs and FPGAs for SpaceX’s Starshield satellite systems, overseeing RTL implementation, verification, and silicon bring-up to deliver high-speed data processing for national security missions.

Asic FPGA Itar Python Tcl +2 skills

190K – 245K $

Physical Design Engineer II (Silicon Engineering)

Open 83d North AmericaFull-time

Designs and implements next-generation ASICs for SpaceX's Starlink network, focusing on physical design steps like synthesis, floorplanning, and place-and-route using industry-standard EDA tools.

Asic Automation Bash Cmos Firmware +4 skills

155K – 210K $

Physical Design Engineer II (Silicon Engineering)

Open 83d North AmericaFull-time

Designs and implements next-generation ASICs for SpaceX’s Starlink network, focusing on physical design steps like synthesis, floorplanning, and timing closure to enable global satellite internet connectivity.

Asic Automation Bash Cmos Firmware +4 skills