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473 jobs

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Skyworks Solutions

RFIC Design | 6-month Summer/Fall Co-op (June '27 - Dec '27)

Open 26d North AmericaInternship

A 6-month onsite co-op (June–December 2027) at Skyworks' Andover, MA design center, where a university student helps develop and characterize RF/analog integrated circuits and Wi-Fi front-end modules through hands-on lab measurements, data analysis, and new product engineering. Suited to EE/physics students with an interest in RF, microwave, and analog IC design.

Cadence Virtuoso

Skyworks Solutions

Analog IC Design Co-Op (Winter/Spring 2027)

Open 23d North AmericaInternship

A Winter/Spring 2027 co-op (January–May, onsite in Cedar Rapids, IA) for enrolled BS/MS/PhD EE students to design reusable analog IC blocks — charge pumps, bandgap references, op-amps, DACs — for cellular phone chips. You'll work with a mentor, build and debug simulation test benches in Cadence Virtuoso/SPICE, and present design reviews.

Automation Cadence Virtuoso Cmos Oscilloscope Python +1 skills

Skyworks Solutions

RF Circuit Design Winter/Spring Co-Op (Jan-June '27)

Open 19d North AmericaInternship

A six-month co-op in Andover, MA helping Skyworks' RF design team develop 2-8 GHz RF/microwave front-end ICs and modules: running circuit, EM, and thermal simulations, lab characterization and debugging, and reporting results. Key tools include Keysight ADS, Cadence Virtuoso, Ansys HFSS, and MATLAB/Python.

Ansys Cadence Virtuoso MATLAB Oscilloscope Python

Principal Analog IC Design Engineer

Open 17d HybridNorth AmericaPrincipal

Leads architecture, transistor-level design, simulation, and validation of high-performance analog power management ICs (DC-DC converters, PMICs) in Qorvo's Power Management division, collaborating with layout, test, and global design teams. Hybrid role onsite multiple days a week in Richardson, TX or San Jose, CA; tools include Cadence Virtuoso, Simplis, and ADS.

Automation Cadence Virtuoso

170K – 222K $

jobs.teradyne.com

Senior Silicon Photonics PIC Design Engineer (SiPh Test Solutions, Haifa, Israel)

NewBe an early applicant Senior

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works…

Ansys Automation Cadence Virtuoso Python

JDA WMS PTE. LTD.

Analog IC Design Engineer

NewBe an early applicant APAC

Designs and develops analog and mixed-signal ICs for power management and smart switch applications, implementing blocks like LDOs, bandgap references, ADCs, charge pumps, and oscillators from concept through silicon validation. Requires 4+ years of analog IC design experience and EDA tools such as Cadence Virtuoso, Spectre, or HSPICE; posted via a Singapore staffing agency.

Cadence Virtuoso

Skyworks Solutions

Staff Electrical Engineer

NewBe an early applicant Staff

Description If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the…

Automation Cadence Virtuoso Cmos MATLAB Networking +3 skills

Omni Design Technologies

EDA CAD Engineer - Mixed Signal IC Design

NewBe an early applicant On-siteAPACFull-time

Omni Design Technologies is hiring an EDA CAD engineer in Hyderabad to build and maintain CAD tools and flows for mixed-signal IC design teams. Day to day involves expert-level Cadence SKILL/SKILL++ scripting, Python automation for design data processing, debugging EDA tools like Virtuoso and Spectre, and managing licenses, version control, and compute infrastructure.

AI Automation Bash CAD Cadence Virtuoso +11 skills

Hong Kong Applied Science and Technology Research Institute

Director, RFS

NewBe an early applicant On-siteAPACFull-time

Hong Kong SAR China

Hong Kong Applied Science and Technology Research Institute (ASTRI) is founded in 2000 by the Government of the Hong Kong Special Administrative Region. As Hong Kong’s largest government-funded research and development…

AI Cadence Virtuoso Cmos MATLAB

SECURE IC - France

Custom Layout Designer (Analog Layout Designer)

NewBe an early applicant On-siteNorth AmericaFull-time

A custom analog layout designer at Cadence's IP Group creates high-speed, high-accuracy CMOS analog/mixed-signal IP blocks for consumer, industrial, and automotive markets — handling the full back-end flow from floorplanning to rule verification in advanced FinFET and gate-all-around nodes, while collaborating with global circuit designers and Cadence Virtuoso R&D.

Cadence Virtuoso Cmos

Analog and Mixed-Signal Modelling Architect (Masters or PhD New Grad)

NewBe an early applicant North AmericaFull-timeJunior

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and…

AI Cadence Virtuoso Confluence C++ Firmware +7 skills

Micron Technology

Senior Design Verification Engineer

NewBe an early applicant North AmericaFull-timeSenior

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…

Agentic AI AI Automation Bash CAD +11 skills

RF Electrical Engineer II - Onsite

NewBe an early applicant On-siteNorth AmericaFull-time

Date Posted: 2026-10-16&#xa;&#xa; Country: United States of America&#xa;&#xa; Location: US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02&#xa;&#xa; Position Role Type: Onsite&#xa;&#xa;…

Ansys Assembly Cadence Virtuoso C++ LabVIEW +4 skills

Principal Systems Engineer, Signal-Path Performance & Modeling

NewBe an early applicant On-siteNorth AmericaFull-timePrincipal

Owns the end-to-end quantitative performance model of Neurophos's optical vector-matrix multiplication engine: building link/power budgets, behavioral models, and Monte Carlo simulations, and allocating accuracy/SNR targets across optical, analog, and digital domains. Core tools are Python (NumPy/SciPy) and MATLAB/Simulink for modeling a silicon-photonics AI inference chip.

AI Cadence Virtuoso Ethernet MATLAB Networking +7 skills

245K – 285K $

Quantum Design Enablement Engineer

Open 25d North AmericaContract

IonQ is hiring a Quantum Design Enablement Engineer to join its Manufacturing team in College Park, MD, acting as the technical bridge between internal quantum chip designers and external foundry partners. Day-to-day work centers on tapeout management, physical verification (DRC/LVS/ERC), hands-on layout and reticle assembly, and refining the Process Design Kit using tools like Calibre, Cadence Vi

Assembly Cadence Virtuoso Cloud Cmos Cybersecurity +5 skills

127K – 166K $

Samsung Semiconductor

Staff Engineer, SRAM Circuit Design

NewBe an early applicant North AmericaFull-timeStaff

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology…

AI Automation Cadence Virtuoso Candidate Experience Perl +3 skills

Senior Photonics Circuit Design Engineer

NewBe an early applicant North AmericaFull-timeSenior

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of…

AI Automation Cadence Virtuoso HPC Python +1 skills

Analog Design Engineer

New On-siteAPACFull-timeIntern

Analog Devices is hiring an Analog Design Engineer in Taiwan to design, simulate, and validate high-speed SerDes and wireline communication circuits in its High-Speed Connectivity group. Day-to-day work spans transistor-level design in Cadence Virtuoso, PVT/Monte Carlo verification, layout collaboration, and silicon bring-up, with growing use of AI-assisted engineering workflows.

AI Automation Cadence Virtuoso Cmos Generative AI +5 skills

RO61 NXP Semiconductors Romania SRL

Lead I/O Design Engineer

New On-siteAPACFull-timeLead

Key Responsibilities Design and develop custom IO circuits including: GPIO LVDS LVCMOS SSTL HSTL DDR Interfaces High-speed SerDes support circuits Perform transistor-level design and simulation using advanced CMOS…

AI Cadence Virtuoso Cmos Ethernet Machine Learning +5 skills

Advanced Micro Devices, Inc

Silicon Design Engineer

Designs and verifies electrostatic-discharge protection circuits for advanced ASIC/FPGA chips using SPICE simulations, layout reviews, and foundry PDKs.

AI Cadence Virtuoso Cloud FPGA Go-to-Market