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Intern verifying RISC-V and AI accelerator SoCs using SystemVerilog, UVM, and Python to ensure functional correctness and robustness.
Develop scalable verification infrastructure and software for high-performance RISC-V CPUs using C++, Python, and SystemVerilog. Responsibilities include building testbenches, optimizing Verilog for simulation and FPGA emulation, and maintaining CI/CD pipelines.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
Leads a team of Verification Engineers to shape test strategies for AI hardware, validating functionality and performance of AI cores. Core technologies include AI-specific data types, compute patterns, on-chip network validation, UVM, SystemVerilog, and cocotb.
Develops and maintains hardware emulation infrastructure for chip design teams, integrating transactors and writing Python/C++ test frameworks to validate silicon before tape-out.
Design Verification Engineer for automotive robotics at Tenstorrent, building and executing verification plans for high-performance RISC-V CPUs and AI accelerators using SystemVerilog, UVM, and formal methods.
Lead the definition and RTL implementation of datacenter-class System IP (MMUs, interconnects, memory controllers, peripherals) for Tenstorrent's next-generation AI/RISC-V SoCs. Hands-on technical leadership in Verilog/SystemVerilog with protocols like AXI, PCIe, DDR, and USB, based hybrid in Bangalore.
Design RTL for power management, interrupt controllers, and interconnects in RISC-V/ARM SoCs, optimizing for performance and power efficiency.
Designs and optimizes high-performance RTL for AI hardware, focusing on micro-architectures, power efficiency, and performance in a hybrid Belgrade office.
Design Verification Engineer builds and runs tests for AI-native compute cores and RISC-V CPUs using SystemVerilog, Python, and CI pipelines to ensure hardware correctness before tape-out.
Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller and support multi-chip integration. The role involves designing test plans, building verification infrastructure, and debugging hardware/software flows using SystemVerilog, UVM, and C/C++.
Designs and implements FPGA-based digital signal processing systems for high-precision analytical instruments using Verilog/VHDL and Xilinx tools in Santa Clara, CA.
Designs and verifies custom silicon for autonomous vehicles, using UVM/SystemVerilog to validate hardware functionality and performance in a hybrid work environment.
Designs and optimizes high-performance machine learning hardware and software for autonomous driving, focusing on ML accelerators and system architectures.
Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo…
Design next-gen SoCs for autonomous vehicles, defining hardware specs and RTL while optimizing performance, power, and latency for Waymo’s compute platform.
Designs high-performance ML ASICs for autonomous driving, translating requirements into hardware features and optimizing power, area, and performance.
Designs and implements RTL for the FPGA configuration controller in AMD's Adaptive SoCs, owning specs and driving blocks from concept through production silicon — coding, lint/CDC, synthesis, timing, verification, DFT, and physical design integration — using Verilog/SystemVerilog, AMBA interconnects, and standard ASIC CAD tools.
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