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Intern designs and optimizes high-performance CPU and AI chips, working through synthesis to tapeout using tools like PnR and timing analysis.
Leads AI/ML-driven physical design flows for semiconductor IP, optimizing RTL-to-GDS methodologies to improve performance, power, and area (PPA) and runtime across advanced nodes.
Own synthesis and place-and-route for high-speed CPU chiplets in advanced AI silicon using Synopsys/Cadence tools.
Full-chip physical design verification engineer ensuring manufacturable silicon for AI SoCs using DRC/LVS/ERC flows and advanced nodes (7nm–3nm).
Designs and implements high-performance CPU and AI/ML chip blocks from synthesis to tapeout, optimizing power, performance, and area using advanced EDA tools and methodologies.
Physical Design Engineer owning Die-to-Die interface implementation from RTL to GDSII for advanced-node chiplet architectures, using full PD flow (synthesis, P&R, CTS, sign-off) with Synopsys/Cadence/Mentor EDA tools and Tcl/Python automation.
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
A Staff Engineer in Physical Design role at Tenstorrent, responsible for implementing high-performance blocks for CPU and AI/ML architectures, from synthesis to tapeout, optimizing performance, power, and area.
Implement physical design for RISC-V CPUs and AI architectures, owning the flow from synthesis to tapeout to optimize performance, power, and area.
Lead the definition and RTL implementation of datacenter-class System IP (MMUs, interconnects, memory controllers, peripherals) for Tenstorrent's next-generation AI/RISC-V SoCs. Hands-on technical leadership in Verilog/SystemVerilog with protocols like AXI, PCIe, DDR, and USB, based hybrid in Bangalore.
Build and own RTL-to-GDSII flows for AI accelerators and CPUs, automating PPA exploration and signoff to speed IP delivery across nodes and variants.
Owns end-to-end physical design of AI accelerator IP blocks, from synthesis to GDSII signoff, ensuring PPA targets and customer timelines are met.
Senior engineer on AMD's Silicon CAD team building and maintaining physical design CAD flows and automation for next-gen CPU, GPU, APU, AI, and SoC chips. Day-to-day involves EDA tool deployment and qualification (Synopsys Fusion Compiler, IC Compiler II, PrimeTime), PPA debugging, regression infrastructure, and TCL/Python automation; hybrid role in Austin, TX.
Mid-level C++ developer role in Pune writing, debugging and profiling software, with object-oriented design in C++ and Python, Git, and Tcl/Tk scripting. Plus points for parallel programming, OpenGL/CUDA and CAD/CAE domain knowledge.
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't…
Description Microchip’s Data Center Solutions Business Unit (DCS) delivers industry leading performance, reliability, and security in Storage Controllers, Memory Controllers, NVMe SSD Controllers, PCIe Switches and SAS…
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