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Principal FPGA Design Engineer Location: Oxford Permanent Oxford Nanopore Technologies : Our goal is to bring the widest benefits to society through enabling the analysis of anything, by anyone, anywhere. The company…
Chips Talk, We Listen proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we…
Designs and implements RTL for custom AI accelerator and SoC silicon in SystemVerilog, owning architecture, micro-architecture, timing closure (STA), and PPA, while collaborating with compiler, performance modeling, verification, and physical design teams. Based in Palo Alto, CA or Austin, TX.
Hardware performance engineer at River AI who builds high-fidelity C++/SystemC simulators and performance models for custom AI accelerator silicon, runs micro-architectural 'what-if' studies, characterizes AI workloads, and correlates models against RTL/FPGA emulators while co-designing with compiler, kernel, and RTL teams.
Design verification engineer ensuring River AI's custom AI silicon is functionally correct: defining verification plans, building UVM/SystemVerilog test benches, coverage models, formal proofs, and emulation environments (ZeBu/Palladium), while collaborating with RTL, performance, and compiler teams.
Job Details: Job Description: About the role Altera is looking for a hands-on Senior RTL Design Engineer to lead FPGA design and platform enablement for Altera development kits. This role spans architecture,…
Job DescriptionJob Description Explore Your Career Possibilities At Talent101, your talent can make a difference. We connect skilled engineering and technology professionals with challenging opportunities where their…
Oversees the full hardware development lifecycle for a next-gen energy-efficient processor, managing schedules, cross-functional teams, and risk mitigation from architecture to production release, with deep engagement in RTL, verification, physical design, and foundry partnerships.
Experienced RTL/microarchitecture engineer at AMD designing core clocking, reset, and power management IP for next-gen Ryzen, Threadripper, and Epyc CPUs. Day to day: writing Verilog/SystemVerilog RTL and C/C++ control firmware, running lint/CDC checks, and debugging across architecture, verification, physical design, and firmware teams.
Systems engineer supporting model-based systems engineering for Bolt Graphics' SoC/IP development: defining ASIC system requirements, analyzing microarchitecture trade-offs (NoC, caches, memory controllers, coherency), and building executable models, simulations, and analytical workflows. Core skills: MBSE, MATLAB/Simulink, and Python/Java/JavaScript.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Are you ready to revolutionise the world with TEKEVER? At TEKEVER, we lead innovation in Europe as the European leader in unmanned technology, where cutting-edge advancements meet unparalleled innovation. Digital |…
Own calibration architecture, bring-up, and lab verification of Neurophos' optical vector-matrix multiplication engine for its silicon-photonics AI chips — devising control-theory/signal-processing algorithms to correct phase, amplitude, and timing across channels, then hands-on bench characterization, mostly with Python/MATLAB.
Overview onsemi is seeking an experienced Staff Digital Design Engineer to join our Core Platform IP organization in Cork, Ireland. This role focuses on the development of digital controllers and digital-on-top…
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Qualcomm is a company of inventors pushing the boundaries of high‑performance compute. Building…
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI,…
Role Summary: Lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications. Drive product execution from concept through…
NVIDIA is looking for a Senior Chip Design Engineer to join our Network Adapter Silicon group. As a Senior Design Engineer at NVIDIA Networking Silicon team, you will join a group of passionate engineers to design and…
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